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首页> 外文期刊>Journal of Low Power Electronics >On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores
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On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores

机译：降低具有未封装内核的SoC的转换延迟故障测试的峰值捕获功率的研究

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摘要

In the nanometer VLSI technologies, delay defects are a predominant concern among test community, and transition delay testing has become the de-facto standard for improving the quality of shipped parts. Scan-based transition delay testing possess several challenges: (a) increase in pattern count, resulting in increased test application time and test pattern volume, (b) need for test compression solutions arising due to the above reason, resulting in area, performance, and power overheads, (c) higher average power during test application, and (d) higher peak power dissipation during test application. Higher-than-normal peak power dissipation during scan capture can lead to a potential yield loss since the power droop can result in higher delays in the gates along a critical path and an otherwise good chip can fail the delay tests. An abnormally high peak power can also reduce the reliability of the chip. In this paper, we explore ways to reduce the peak capture power during transition delay testing of core-based systems-on-chip (SoC). We argue that the residual test mode, which can involve a significant portion of the flip-flops in the circuit, is the root cause for the issues arising in the transition delay testing of SoC, especially when the cores are not wrapped. We propose a way to analyze the interaction among cores and introduce partial residual test modes to get adequate fault coverage; the partial residual test modes include a much smaller number of flops than the full residual test mode, thereby resulting in a lower peak power, lower test volume, lower test application time, and lower test cost. We call this architecture as Quiet and Optimized Divide-and-Conquer scan architecture. Experiments on an industrial ASIC reveals that the proposed technique reduces the peak capture power by 50.5% and the average test power by 45.6%, while achieving 71.7% reduction in test application time.
机译：在纳米级VLSI技术中，延迟缺陷是测试界最关注的问题，过渡延迟测试已成为提高运输零件质量的实际标准。基于扫描的过渡延迟测试面临几个挑战：（a）模式数量增加，导致测试应用时间和测试模式体积增加;（b）由于上述原因而需要测试压缩解决方案，从而导致面积，性能，和电源开销，（c）在测试应用期间更高的平均功率，以及（d）在测试应用期间更高的峰值功耗。扫描捕获过程中峰值功率消耗高于正常值可能会导致潜在的良率损失，因为功率下降会导致沿关键路径的栅极出现更高的延迟，否则良好的芯片可能无法通过延迟测试。异常高的峰值功率也会降低芯片的可靠性。在本文中，我们探索了在基于内核的片上系统（SoC）的过渡延迟测试过程中降低峰值捕获功率的方法。我们认为残留测试模式可能会涉及电路中的大部分触发器，这是SoC转换延迟测试中出现问题的根本原因，尤其是在未包装内核的情况下。我们提出了一种分析核之间相互作用的方法，并引入了部分残差测试模式以获得足够的故障覆盖率;与全部残余测试模式相比，部分残余测试模式的触发器数量少得多，从而导致更低的峰值功率，更低的测试量，更低的测试应用时间以及更低的测试成本。我们将此架构称为“安静且优化的分而治之”扫描架构。在工业ASIC上进行的实验表明，该技术将峰值捕获功率降低了50.5％，将平均测试功率降低了45.6％，同时将测试应用时间缩短了71.7％。

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