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A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics

机译:一种基于知识的智能预加载支持的方式高速缓存锁定方案,可有效用于低功耗多核电子产品

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摘要

Adopting multicore architecture in consumer and bio-inspired electronics is promising to fulfill the growing need of high-performance. However, multi-level caches in multicore architecture require significant amount of power to be operated. In such a multi-level cache system, parallel thread execution becomes extremely difficult, which may also cause performance detraction. Studies suggest that cache locking has potential to decrease total power consumption and increase performance by reducing cache misses. In this work, a promising cache locking strategy for multicore electronics is proposed. According to this strategy, preselected blocks are preloaded knowingly at shared level cache and way cache locking is performed to lock all or some of those blocks. We model two multicore architectures - one Xeon-like quad-core system where CL2 is shared and one Opteron-like quad-core system where CL3 is shared. Popular MPEG-4, MPEG-3, JPEG, GIF, and FFT applications are used to run the simulation programs. Experimental results suggest that the proposed cache locking strategy is beneficial for designing low-power cache memory subsystem for multicore devices. Using proposed cache locking scheme, power consumption per task and mean delay per task are decreased by 41.12% and 35.51%, respectively, for MPEG-4 workload.
机译:在消费类和受生物启发的电子产品中采用多核架构有望满足日益增长的高性能需求。但是,多核体系结构中的多级缓存需要大量的电源才能运行。在这样的多级缓存系统中,并行线程执行变得极为困难,这也可能导致性能下降。研究表明,缓存锁定可以通过减少缓存未命中来降低总功耗并提高性能。在这项工作中,提出了一种有前途的多核电子设备缓存锁定策略。根据该策略,预先选择的块在共享级缓存中被有意识地预加载,并且执行缓存锁定的方式来锁定所有或某些那些块。我们对两种多核架构进行了建模-一种共享CL2的类似Xeon的四核系统,以及共享CL3的一种类似Opteron的四核系统。流行的MPEG-4,MPEG-3,JPEG,GIF和FFT应用程序用于运行仿真程序。实验结果表明,所提出的高速缓存锁定策略有利于设计用于多核设备的低功耗高速缓存存储器子系统。使用建议的缓存锁定方案,对于MPEG-4工作负载,每个任务的功耗和每个任务的平均延迟分别降低了41.12%和35.51%。

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