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首页> 外文期刊>Journal of Low Power Electronics >Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling
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Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling

机译：用于竞争感知任务迁移和频率缩放的芯片多处理器性能建模

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Workload consolidation is usually performed in datacenters to improve server utilization for higher energy efficiency. One of the key issues in workload consolidation is the contention for shared resources. Dynamic voltage and frequency scaling (DVFS) of CPU is another effective technique that has been widely used to trade performance for power reduction. We have found that the degree of resource contention of a system affects its performance sensitivity to CPU frequency. Without detailed architecture level information, the complex relationship between contention, frequency and performance cannot be retrieved analytically. In this paper, we apply machine learning techniques to construct a model for chip multiprocessor (CMP) Performance Estimation under Fixed workload Scheduling (PEFS). It quantifies performance degradation of target process caused by resource contention and frequency scaling for current CMP workload with the assumption of a fixed task mapping. The model is further generalized for performance prediction with task migration (PPTM), which predicts the performance degradation after potential intra-processor task migration. Both models are tested on an SMT-enabled chip multi-processor with 10～20% estimation error on average. Experimental results show that our PEFS model can keep the performance of those bottleneck tasks much closer to the performance threshold than all other techniques, which leads to almost no performance violation while achieves more energy savings, and task migration guided by our PPTM model produces 4%～9% higher performance than conventional task migration guided by last level cache miss.
机译：通常在数据中心执行工作负载合并，以提高服务器利用率以提高能源效率。工作负载合并中的关键问题之一是共享资源的争用。 CPU的动态电压和频率缩放（DVFS）是另一项有效的技术，已广泛用于降低性能的交易中。我们发现，系统的资源争用程度会影响其对CPU频率的性能敏感性。没有详细的体系结构级别信息，就无法解析地检索出竞争，频率和性能之间的复杂关系。在本文中，我们应用机器学习技术来构建固定工作负荷调度（PEFS）下的芯片多处理器（CMP）性能估计模型。在固定任务映射的假设下，它量化了由于当前CMP工作负载的资源争用和频率缩放而导致的目标进程的性能下降。该模型可进一步推广用于任务迁移（PPTM）的性能预测，该模型可预测潜在的处理器内任务迁移后的性能下降。两种型号均在具有SMT功能的芯片多处理器上进行了测试，平均估计误差为10〜20％。实验结果表明，与所有其他技术相比，我们的PEFS模型可以使那些瓶颈任务的性能保持更接近性能阈值的水平，这几乎不会导致性能违规，同时还可以节省更多能源，而以PPTM模型为指导的任务迁移可产生4％的性能在上一级缓存未命中的指导下，性能比传统任务迁移高约9％。

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