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首页> 外文期刊>Journal of Low Power Electronics >A Design Approach for Efficient Multipliers for Wearable Technology
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A Design Approach for Efficient Multipliers for Wearable Technology

机译：穿戴式技术高效乘数的设计方法

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The body area network is a wireless sensor network used for medical diagnosis. With such a network, continuous health monitoring is performed to provide real-time feedback. Designing of such devices are a challenge as size of wearable technology (Ear hearing aid) is decreasing while demand for performance at low power consumption is increasing. To meet these challenges, power critical blocks of such devices are custom designed. For biomedical sensor networks and DSP chips, multipliers are the key. At circuit level for wearable technology like ear aids, low power and area efficient arithmetic components are required to meet the challenges. In this paper, we propose an efficient, low power, n × n bit multiplier design for power-critical applications. An efficient 2 × 2 bit multiplier cell is proposed that uses only 36 MOS transistors compared to 52 used for conventional 2 × 2 multiplier and is tested at 625 MHz (0.18 μm and 1.8 V) for its functionality and full swing outputs. General cell based multiplier algorithm is described and used for making proposed 4 × 4 multiplier with the proposed 2 × 2 bit multiplier cell. Proposed 4 × 4 bit multiplier consumes 36% less power, 23% faster and shows 50% better power-delay-product (PDP) compared to conventional Wallace multiplier at 100 MHz. With the proposed 4 × 4 multiplier, full scale rail to rail output with reduced glitches has been observed when tested at 10-100 MHz, 0.18 μm and 1.8 V. Modular architectures of power gated larger multipliers (8 × 8 and 16 × 16), based upon proposed cells are also discussed.
机译：人体局域网是用于医学诊断的无线传感器网络。通过这样的网络，可以进行连续的运行状况监视以提供实时反馈。由于可穿戴技术（耳助听器）的尺寸在减小，而对低功耗性能的需求却在增加，因此设计此类设备是一项挑战。为了应对这些挑战，此类设备的电源关键模块是定制设计的。对于生物医学传感器网络和DSP芯片，乘法器是关键。在可穿戴技术（如助听器）的电路级，需要低功耗和高效面积的算术组件来应对挑战。在本文中，我们提出了一种针对功率关键型应用的高效，低功耗，n×n位乘法器设计。提出了一种高效的2×2位乘法器单元，与传统的2×2乘法器中使用的52个MOS晶体管相比，仅使用36个MOS晶体管，并在625 MHz（0.18μm和1.8 V）下对其功能和全摆幅输出进行了测试。描述了基于通用单元的乘法器算法，并将其用于使用建议的2×2位乘法器单元制作建议的4×4乘法器。提议的4×4位乘法器与传统的Wallace乘法器在100 MHz时相比，功耗降低了36％，速度降低了23％，并显示出50％的功率延迟乘积（PDP）。使用建议的4×4乘法器，在10-100 MHz，0.18μm和1.8 V下进行测试时，可以观察到满幅轨到轨输出，并具有降低的毛刺。功率门控较大乘法器（8×8和16×16）的模块化架构，还基于建议的单元格进行了讨论。

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