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首页> 外文期刊>Journal of Low Power Electronics >A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates
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A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates

机译：利用新型两个晶体管（2T）XOR门的高速，低功耗8位×8位乘法器设计

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The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit × 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and engineering the threshold voltage of the MOS transistor through appropriate biasing and device geometry. Using the 2T XOR gates, a full adder has been realised. Detailed simulations have been carried out to compare the proposed 2T XOR gate and 6T full adder against the existing XOR gates and full adders available in literature with respect to power delay product (PDP), noise margin and area. A significant improvement of PDP, area and noise margin has been obtained with the 2T XOR gate with respect to the existing XOR gates. An 8 bit × 8 bit multiplier has also been implemented using the design of 6T adder and its performance has been analysed and compared with similar multipliers designed with peer adders design available in literature. Simulation studies have been carried out using UMC 65-nm, 90-nm and 130-nm CMOS process technologies in Cadence Spectre along-with process, voltage and temperature (PVT) variation analysis. The power delay product (PDP) of the proposed multiplier has been found to be as low as 1.854 pJ using UMC 65-nm CMOS process. The design of the 8 bit × 8 bit multiplier has been extended to the design of 8 bit multiply-accumulate (MAC) unit, which has been simulated using 65-nm CMOS process. A delay of 3.977 ns and power dissipation of 1.107 mW has been obtained with the MAC unit. The proposed XOR gate is also evaluated through independent gate (IG) mode FINFETs in 32-nm technology as a substitute to CMOS technology.
机译：本文提出了一种新颖的两晶体管（2T）XOR门设计及其在设计8位×8位乘法器中的应用。该设计探索了适当偏置MOS晶体管并通过适当偏置和器件几何结构来设计MOS晶体管的阈值电压的本质。使用2T XOR门，已经实现了完整的加法器。已经进行了详细的仿真，以将建议的2T XOR门和6T全加器与现有的XOR门和文献中有关功率延迟乘积（PDP），噪声容限和面积的全加器进行比较。与现有的XOR门相比，使用2T XOR门可获得PDP，面积和噪声容限的显着改善。还使用6T加法器的设计实现了8位×8位乘法器，并对其性能进行了分析，并与文献中采用对等加法器设计的类似乘法器进行了比较。已经在Cadence Spectre中使用UMC 65-nm，90-nm和130-nm CMOS工艺技术以及工艺，电压和温度（PVT）变化分析进行了仿真研究。使用UMC 65-nm CMOS工艺，已发现拟议乘法器的功率延迟乘积（PDP）可低至1.854 pJ。 8位×8位乘法器的设计已扩展到8位乘法累加（MAC）单元的设计，该单元已使用65 nm CMOS工艺进行了仿真。使用MAC单元获得了3.977 ns的延迟和1.107 mW的功耗。还通过32纳米技术中的独立栅极（IG）模式FINFET对拟议的XOR栅极进行了评估，以替代CMOS技术。

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