Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter

D. N. Jagadish; M. S. Bhat

首页> 外文期刊>Journal of Low Power Electronics >Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter

【24h】

Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter

机译：基于低能量和面积有效的非二进制电容器阵列的逐次逼近寄存器模数转换器

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

In this paper, we propose a low energy consumption and area efficient successive approximation register analogue-to-digital converter. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array in comparison to other nonbinary capacitor array based successive approximation register analogue-to-digital converters. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside capacitor array, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time.

机译：在本文中，我们提出了一种低能耗，高面积效率的逐次逼近寄存器模数转换器。与其他基于非二进制电容器阵列的逐次逼近寄存器模数转换器相比，该方法可节省大量的开关能量并减少电容器阵列中使用的总电容。本技术采用两个执行无源电荷重新分配的电容器阵列。新颖的电容器阵列架构通过平衡电容器阵列内部电荷共享节点处的寄生效应，将寄生效应对电荷共享过程的影响降至最低，并与开关算法结合使用，可在不大大影响转换时间的情况下降低能耗和面积。

著录项

来源
《Journal of Low Power Electronics》 |2015年第3期|共8页
作者
D. N. Jagadish; M. S. Bhat;
展开▼
作者单位

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
Successive Approximation Register ADC; Nonbinary Capacitor; Unit Capacitor Array; Dual Capacitor Array; Low Energy; Area Efficient ADC;

机译：逐次逼近寄存器ADC;二进制电容器;单位电容器阵列;双电容器阵列;低功耗;高效的ADC;

相似文献

外文文献
中文文献
专利

1. Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter [J] . D. N. Jagadish, M. S. Bhat Journal of Low Power Electronics . 2015,第3期

机译：基于低能量和面积有效的非二进制电容器阵列的逐次逼近寄存器模数转换器
2. 23 ?μW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme [J] . Lei Sun, Chi Tung Ko, Marco Ho, The Journal of Engineering . 2014,第8期

机译：23 µW 8.9有效位数1.1 MS / s逐次逼近寄存器模数转换器，具有节能的数模转换器切换方案
3. Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area [J] . Momeni Mahdi, Yavari Mohammad International journal of circuit theory and applications . 2020,第11期

机译：在连续近似寄存器模数转换器中转换采样输入信号，以减少数模转换器开关能量和区域
4. A time-based successive approximation register analog-to-digital converter using a pulse width modulation technique with a single capacitor [C] . Young-Hwa Kim, SeongHwan Cho SoC Design Conference (ISOCC 2009), 2009 . 2009

机译：基于时间的逐次逼近寄存器模数转换器，使用脉宽调制技术和单个电容器
5. Low-power techniques for Successive Approximation Register (SAR) Analog-to-Digital Converters. [D] . Sekar, Ramgopal. 2010

机译：逐次逼近寄存器（SAR）模数转换器的低功耗技术。
6. An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications [O] . Santosh Koppa, Manouchehr Mohandesi, Eugene John -1

机译：用于生物医学应用的超低功耗电荷重新分配逐次逼近寄存器A / D转换器
7. 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme [O] . Lei Sun, Chi Tung Ko, Marco Ho, 2014

机译：23μW8.9有效位数1.1 ms / s逐次逼近寄存器模数转换器，具有高能效的数模转换器切换方案

Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter

摘要

著录项

相似文献

相关主题

期刊订阅