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首页> 外文期刊>Journal of Low Power Electronics >ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies
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ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies

机译：基于ARTL的非异构标准单元ASIC技术的硬件综合

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Register-Transfer Level (RTL) modeling and synthesis is a crucial part of digital system design. The constantly growing complexities of today's data processing systems make it more and more complicated to manage the RTL intent, timing, resource requirement and power-consumption of the macrocells in complex System-on-Chips (SoCs). Although there are numerous applications where the rapid prototyping is the primary objective; therefore, high level synthesis methods may be used to handle complexity and reduce design time but in case of highly timing-critical, resource-critical and/or power-consumption-critical applications the hand-crafted RTL design and time-consuming optimization is unavoidable. In this paper a new extension to RTL design and a specific synthesis method are introduced, which make a reduced design time achievable while supporting low-level micro-architectural optimization. The results of the investigations for design and synthesis efficiency are also presented with respect to the non-heterogeneous standard cell ASIC technologies.
机译：寄存器传输级（RTL）建模和综合是数字系统设计的关键部分。当今数据处理系统的复杂性不断增长，使得在复杂的片上系统（SoC）中管理RTL的意图，时序，资源要求和宏单元的功耗变得越来越复杂。尽管在众多应用中，快速原型设计是主要目标;因此，可以使用高级综合方法​​来处理复杂性并减少设计时间，但是在高度时序关键，资源关键和/或功耗关键的应用中，手工RTL设计和费时的优化是不可避免的。本文介绍了对RTL设计的新扩展和一种特定的综合方法，在支持低级微体系结构优化的同时，可以缩短设计时间。还针对非异构标准单元ASIC技术介绍了设计和合成效率的研究结果。

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