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Design and Synthesis of HDL Code Based on High Level FPGA Design Flow for SDR Model

机译:基于高级SDR模型的FPGA设计流程的HDL代码的设计与综合

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摘要

There has been considerable recent interest in defining a Hardware Abstraction Layer (HAL) to facilitate code reuse in the signal processing subsystems of software-defined radios. HDL for FPGA-based signal processing is a significant aspect of such HAL efforts. In this study, we show how a platform-based approach to FPGA design that provides a high level of design abstraction can also provide the ability to target multiple FPGA families from a single source model. The approach combines direct mapping of a Simulink model with code generation of register-transfer level HDL. By exploiting retiming and other optimizations available through logic synthesis, it is possible to obtain very efficient realizations of signal processing functions. This research complements HAL recommendations by focusing on mechanisms, guidelines and methodologies for constructing signal processing functions in FPGAs. It helps to address requirements for executable specifications as well as providing source that can be compiled though automatic code generation. At last, this new design technique would help in designing and realizing SDR-3G wireless communication system and accelerate the transition to 4G wireless communication system.
机译:最近,人们对定义硬件抽象层(HAL)以促进软件定义的无线电的信号处理子系统中的代码重用感兴趣。用于基于FPGA的信号处理的HDL是此类HAL努力的重要方面。在这项研究中,我们展示了提供高水平设计抽象的基于平台的FPGA设计方法如何还可以提供从单一源模型针对多个FPGA系列的能力。该方法将Simulink模型的直接映射与寄存器传输级HDL的代码生成结合在一起。通过利用时序重排和其他通过逻辑综合获得的优化,可以非常有效地实现信号处理功能。这项研究的重点是在FPGA中构建信号处理功能的机制,指南和方法,从而对HAL建议进行了补充。它有助于满足可执行规范的要求,并提供可以通过自动代码生成进行编译的源。最后,这项新的设计技术将有助于设计和实现SDR-3G无线通信系统,并加速向4G无线通信系统的过渡。

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