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首页> 外文期刊>Journal of Micromechanics and Microengineering >Membrane covered electrically isolated through-wafer via holes
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Membrane covered electrically isolated through-wafer via holes

机译:膜覆盖电隔离通孔的通孔

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An electrically isolated through-wafer via hole, covered by a membrane, has been realized by standard integrated circuits processes together with deep silicon etching. The deep silicon etching was performed by the Bosch silicon etch process in a Plasma-Therm etch system. The via structures were made in double-sided polished 300 mum thick silicon wafers and had widths down to 20 mum, which correspond to an aspect ratio of 15. The fact that the via structures are electrically isolated makes them a suitable start-point to realize interconnections through a wafer. Furthermore, the application field of the via structure is broadened by the flexibility in the design of the structure, which makes it possible to apply an almost arbitrary membrane material onto the via structure at the end of the process. [References: 15]
机译:通过标准集成电路工艺以及深硅蚀刻,已经实现了一个被膜覆盖的电绝缘通孔通孔。通过等离子-热蚀刻系统中的博世硅蚀刻工艺执行深硅蚀刻。通孔结构是在300微米厚的双面抛光硅晶片中制成的,宽度低至20微米,对应于15的纵横比。通孔结构被电隔离的事实使其成为实现的合适起点。通过晶圆的互连。此外,通孔结构的设计领域的灵活性拓宽了通孔结构的应用领域,这使得可以在工艺结束时将几乎任意的膜材料施加到通孔结构上。 [参考:15]

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