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首页> 外文期刊>Journal of systems architecture >Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches
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Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches

机译：具有专用L2高速缓存的芯片多处理器的可重用性感知高速缓存共享

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摘要

In this paper, we propose a novel on-chip L2 cache organization for chip multiprocessors (CMPs) with private L2 caches. The proposed approach, called reusability-aware cache sharing (RACS), combines the advantages of both a private L2 cache and a shared L2 cache. Since a private L2 cache organization has a short access latency, the RACS scheme employs a private L2 cache organization. However, when a cache block in a private L2 cache is selected for eviction, RACS first evaluates its reusability. If the block is likely to be reused in the near future, it may be saved to a peer L2 cache which has space available. In this way, the RACS scheme effectively simulates the larger capacity of a shared L2 cache. Simulation results show that RACS reduced the number of off-chip memory accesses by 24% compared to a pure private L2 cache organization on average for the SPIASH 2 multi-threaded benchmarks, and by 16% for multi-programmed benchmarks.
机译：在本文中，我们为具有私有L2缓存的芯片多处理器（CMP）提出了一种新颖的片上L2缓存组织。所提出的方法称为可重用性感知缓存共享（RACS），结合了私有L2缓存和共享L2缓存的优点。由于私有L2缓存组织的访问延迟很短，因此RACS方案采用了私有L2缓存组织。但是，当选择私有L2缓存中的缓存块进行逐出时，RACS首先评估其可重用性。如果该块可能在不久的将来重用，则可以将其保存到具有可用空间的对等L2缓存中。这样，RACS方案有效地模拟了共享L2缓存的更大容量。仿真结果表明，与SPIASH 2多线程基准测试相比，纯纯粹的L2高速缓存组织相比，RACS减少了片外内存访问次数，对于多程序基准测试平均降低了16％。

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