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FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method

机译：有限元方法的稀疏矩阵向量乘法的FPGA体系结构和实现

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The Finite Element Method (FEM) is a computationally intensive scientific and engineering analysis tool that has diverse applications ranging from structural engineering to electromagnetic simulation. The trends in floating-point performance are moving in favor of Field-Progmmmable Gate Arrays (FPGAs), hence increasing interest has grown in the scientific community to exploit this technology. We present an architecture and implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations arising from FEM applications. FEM matrices display specific sparsity patterns that can be exploited to improve the efficiency of hardware designs. Our architecture exploits FEM matrix sparsity structure to achieve a balance between performance and hardware resource requirements by relying on external SDRAM for data storage while utilizing the FPGAs computational resources in a stream-through systolic approach. The architecture is based on a pipelined linear array of processing elements (PEs) coupled with a hardware-oriented matrix striping algorithm and a partitioning scheme which enables it to process arbitrarily big matrices without changing the number of PEs in the architecture. Therefore, this architecture is only limited by the amount of external RAM available to the FPGA. The implemented SMVM-pipeline prototype contains 8 PEs and is clocked at 110 MHz obtaining a peak performance of 1.76 GFLOPS. For 8 GB/s of memory bandwidth typical of recent FPGA systems, this architecture can achieve 1.5 GFLOPS sustained performance. Using multiple instances of the pipeline, linear scaling of the peak and sustained performance can be achieved. Our stream-through architecture provides the added advantage of enabling an iterative implementation of the SMVM computation required by iterative solution techniques such as the conjugate gradient method, avoiding initialization time due to data loading and setup inside the FPGA internal memory. (c) 2007 Elsevier B.V. All rights reserved.
机译：有限元方法（FEM）是一种计算密集型的科学和工程分析工具，具有从结构工程到电磁仿真的多种应用。浮点性能的趋势正朝着现场可编程门阵列（FPGA）的方向发展，因此，科学界对利用该技术的兴趣日益浓厚。我们介绍了一种基于FPGA的稀疏矩阵矢量乘法器（SMVM）的体系结构和实现，可用于由FEM应用产生的大型稀疏方程组的迭代解决方案。 FEM矩阵显示特定的稀疏模式，可以利用这些模式来提高硬件设计的效率。我们的架构利用FEM矩阵稀疏结构，通过依赖外部SDRAM进行数据存储，同时以流式收缩方式利用FPGA的计算资源，从而在性能和硬件资源要求之间取得平衡。该体系结构基于处理元素（PE）的流水线型线性阵列，并结合了面向硬件的矩阵分条算法和分区方案，该方案使它能够处理任意大矩阵而无需更改体系结构中PE的数量。因此，该架构仅受FPGA可用的外部RAM数量的限制。已实现的SMVM流水线原型包含8个PE，时钟频率为110 MHz，峰值性能为1.76 GFLOPS。对于最近的FPGA系统典型的8 GB / s的存储带宽，该架构可以实现1.5 GFLOPS的持续性能。使用管道的多个实例，可以实现峰值的线性缩放和持续的性能。我们的流过架构提供了额外的优势，可以实现迭代解决方案技术（例如共轭梯度法）所需的SMVM计算的迭代实现，避免了由于FPGA内部存储器中的数据加载和设置而导致的初始化时间。 （c）2007 Elsevier B.V.保留所有权利。

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