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Investigation of threshold voltage instability induced by gate bias stress in ZnO nanowire field effect transistors

机译:ZnO纳米线场效应晶体管中栅极偏置应力引起的阈值电压不稳定性的研究

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We investigated the threshold voltage instability induced by gate bias (V _G) stress in ZnO nanowire (NW) field effect transistors (FETs). By increasing the V _G sweep ranges and repeatedly measuring the electrical characteristics of the ZnO NW FETs, the V _G stress was produced in the dielectric layer underneath the ZnO NW. Consequently, the electrical conductance of the ZnO NW FETs decreased, and the threshold voltage shifted towards the positive V _G direction. This threshold voltage instability induced by the V _G stress is associated with the trapping of charges in the interface trap sites located in the ZnO NW-dielectric interface. Our study will be helpful for understanding the stability of ZnO NW FETs during repetitive operations.
机译:我们研究了由ZnO纳米线(NW)场效应晶体管(FET)中的栅极偏置(V _G)应力引起的阈值电压不稳定性。通过增加V _G扫描范围并重复测量ZnO NW FET的电特性,在ZnO NW下方的介电层中会产生V _G应力。因此,ZnO NW FET的电导率降低,并且阈值电压向正V _G方向偏移。由V_G应力引起的该阈值电压不稳定性与电荷在位于ZnO NW-电介质界面中的界面俘获位点中的俘获有关。我们的研究将有助于理解重复操作过程中ZnO NW FET的稳定性。

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