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Dislocation sink annihilating threading dislocations in strain-relaxed Si1-xGex layer

机译：位错沉降湮灭应变松弛的Si1-XGEx层中的穿线脱位

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We proposed a dislocation sink technology for achieving Si1-xGex multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si1-xGex channel. A generation of a dislocation sink via H+ implantations in a strain-relaxed Si0.7Ge0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si0.7Ge0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 degrees C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [Si-I or Ge-I +V-Si or V-Ge -> Si1-xGex] annihilation process, where Si-I, Ge-I, V-Si, and V-Ge are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H+ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 x 10(15) atoms cm(-2) and 800 degrees C.
机译：我们提出了一种用于实现超出5nm晶体管设计规则的Si1-XGex多桥通道场效应晶体管的错位沉降技术，其基本上需要一个几乎晶体缺陷的Si1-XGex通道。通过H +植入在Si基板上生长的应变弛豫Si0.7Ge0.3层中的脱位沉积物的一代脱位沉积物。在Si衬底上生长几乎湮灭，位于宽松的Si0.7Ge0.3层之间的界面附近的完全错入和穿线位错Si衬底。在1.25 MV加速电压下，实时（从室温到600摄氏度到600℃）原位高分辨率 - 透射 - 电子显微镜和反向快速傅里叶变换图像观察明显展示了位错沉降的湮灭过程在热退火过程中剩余的误操作和穿线脱位，称为[Si-i或Ge-i + V-si或V-ge - > Si1-xgex]湮灭过程，其中Si-i，Ge-i，V-Si， V-GE分别是间隙SI，Intertitial GE，SI空缺和GE空位。特别是，湮灭工艺效率大大依赖于H +植入和退火温度的剂量;即，在5×10（15）原子cm（-2）和800℃下实现最大湮灭过程效率。

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