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SOC Test Architecture Design for Efficient Utilization of Test Bandwidth

机译：SOC测试架构设计，可有效利用测试带宽

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This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified parameters of modules and their tests, we design an architecture that minimizes the required tester vector memory depth and test application time. In this article, we formulate the test architecture design problems for both modules with fixed- and flexible-length scan chains, assuming the relevant module parameters and a maximal SOC TAM width are given. Subsequently, we derive a formulation for an architecture-independent lower bound for the SOC test time. We analyze three types of TAM under-utilization that make the theoretical lower bound unachievable in most practical architecture instances. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and TestRail architectures with either serial or parallel test schedules. Experimental results for the ITC'02 SOC Test Benchmarks show that, compared to manual best-effort engineering approaches, we can save up to 75% in test times, while compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
机译：本文讨论了用于测试大型系统芯片（SOC）以模块化方式制造缺陷的片上体系结构的设计。这些体系结构由包装程序和测试访问机制（TAM）组成。对于具有指定模块参数及其测试的SOC，我们设计了一种体系结构，该体系结构可将所需的测试仪向量存储深度和测试应用时间降至最低。在本文中，假设给出了相关模块参数和最大SOC TAM宽度，我们将针对具有固定长度和灵活长度扫描链的两个模块制定测试体系设计问题。随后，我们推导了SOC测试时间与体系结构无关的下限的公式。我们分析了TAM使用不足的三种类型，这些类型在大多数实际体系结构实例中都无法实现理论上的下限。我们提出了一种新颖的与体系结构无关的启发式算法，该算法可以有效地优化给定SOC的测试体系结构。该算法可以有效地确定TAM的数量及其宽度，将模块分配给TAM以及每个模块的包装设计。我们展示了如何使用该算法通过串行或并行测试计划来优化测试总线和TestRail体系结构。 ITC'02 SOC测试基准的实验结果表明，与人工尽力而为的工程方法相比，我们可以节省多达75％的测试时间，而与以前发布的算法相比，我们可以在可忽略的计算量下获得可比或更好的测试时间时间。

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