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首页> 外文期刊>ACM SIGPLAN Notices: A Monthly Publication of the Special Interest Group on Programming Languages >Efficiently Parallelizing Instruction Set Simulation of Embedded Multi-Core Processors Using Region-based Just-in-Time Dynamic Binary Translation
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Efficiently Parallelizing Instruction Set Simulation of Embedded Multi-Core Processors Using Region-based Just-in-Time Dynamic Binary Translation

机译：使用基于区域的即时动态二进制翻译对嵌入式多核处理器进行高效并行指令集仿真

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摘要

Embedded systems, as typified by modern mobile phones, are already seeing a drive toward using multi-core processors. The number of cores will likely increase rapidly in the future. Engineers and researchers need to be able to simulate systems, as they are expected to be in a few generations time, running simulations of many-core devices on today's multi-core machines. These requirements place heavy demands on the scalability of simulation engines, the fastest of which have typically evolved from just-in-time (Jit) dynamic binary translators (Dbt).
机译：以现代手机为代表的嵌入式系统已经在寻求使用多核处理器的驱动力。内核数量将来可能会迅速增加。工程师和研究人员需要能够仿真系统，因为预计它们需要几代人的时间，才能在当今的多核计算机上运行多核设备的仿真。这些要求对仿真引擎的可伸缩性提出了很高的要求，仿真引擎的可伸缩性通常是由即时（Jit）动态二进制转换器（Dbt）演变而来的。

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