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首页> 外文期刊>ACM Transactions on Architecture and Code Optimization >The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing
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The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

机译：适用于多核和众核架构的McPAT框架：同时建模功率，面积和时序

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This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated system components such as memory controllers and Ethernet controllers. At circuit level, McPAT supports detailed modeling of critical-path timing, area, and power. At technology level, McPAT models timing, area, and power for the device types forecast in the ITRS roadmap. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to accurately quantify the cost of new ideas and assess trade-offs of different architectures using new metrics such as Energy-Delay-Area~2 Product (EDA~2P) and Energy-Delay-Area Product (EDAP). This article explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting trade-offs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies from cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clustering gives the best EDA~2P and EDAP.
机译：本文介绍了McPAT，这是一个集成的电源，面积和时序建模框架，该框架支持针对范围从90nm至22nm甚至更高的多核和多核处理器配置的全面设计空间探索。在微体系结构级别，McPAT包括用于完整芯片多处理器基本组件的模型，包括按序和无序处理器内核，片上网络，共享缓存以及诸如存储器控制器和以太网控制器之类的集成系统组件。 。在电路级，McPAT支持关键路径时序，面积和功率的详细建模。在技​​术层面，McPAT为ITRS路线图中预测的设备类型建模时序，面积和功耗。 McPAT具有灵活的XML接口，以方便其与许多性能模拟器一起使用。结合性能仿真器，McPAT使架构师能够使用新的指标（例如，能源延迟面积2产品（EDA〜2P）和能源延迟面积产品）准确地量化新思想的成本，并评估不同架构的权衡。 （EDAP）。本文通过改变几代处理技术的集群化程度，探索了未来多核处理器的互连选项。集群将在区域和性能之间带来有趣的折衷，因为将内核分组为集群所需的互连会产生区域开销，但是由于缓存共享的协同作用，许多应用程序都可以很好地利用它们。将McPAT的功率，面积和时序结果与针对22nm技术的多核设计的PARSEC基准测试的性能仿真相结合，显示8核群集提供了最佳的节能产品，而将裸片面积考虑在内，则4核群集提供最佳的EDA〜2P和EDAP。

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