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Efficient Systolic Array Architecture Design And Implementation For Discrete Wavelet Transform

机译：高效的Systolic阵列架构设计和实现离散小波变换

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The Discrete Wavelet Transform is a signal processing technique in which has found wide acceptance data compression. Considerable work has been done in designing systolic architecture to perform DWT. This paper proposes new systolic array architecture to compute 1-D discrete wavelet transform (DWT). The proposed systolic array consists of L processing elements (PE), where L denotes the number of levels. The major achievement is in power reduction and reduction of hardware complexity. The major contribution is reduction in number of multiplications by 23 after identification of common terms in low-pass and high-pass equations. Additional 16 multiplications are eliminated by using CSD operation for 9/7 bi-orthogonal wavelet filter coefficients. The added wrapper design reduces I/O count and power due to additional I/O. A pipelined hierarchy is designed to process 16 bit of 8 input data and generates 1-D DWT output The proposed architecture reduces number of multiplications from 59 to 20, which causes reduction in dynamic power from 32.4 mW to 10.2 mW. It also reduces I/O count from 83 to 35 by using a Serial in Parallel Out (SIPO) at the input and Parallel In Serial Out (PISO) at the output. The maximum throughput is 2-byte output/cycle. The FPGA (Vertex-2pro) implementation runs at a maximum frequency of 140 MHz. The architecture can easily be extended to generate a 2-D Wavelet transform.
机译：离散小波变换是一种信号处理技术，其中已找到广泛的接受数据压缩。在设计收缩系统架构中进行了相当大的工作来执行DWT。本文提出了新的收缩阵列架构来计算1-D离散小波变换（DWT）。所提出的收缩系统阵列由L处理元素（PE）组成，其中L表示级别的数量。主要成就处于减值和降低硬件复杂性。在识别低通和高通方程中的常见术语之后，在23后，主要贡献减少了乘法数。通过使用CSD操作为9/7双正交小波滤波器系数消除额外的16个乘法。添加的包装器设计由于额外的I / O而降低了I / O计数和功率。流水线层次结构设计为处理16位的8个输入数据，并产生1-D DWT输出，所提出的架构从59到20缩短乘法数，这导致动态功率降低到32.4 MW至10.2 MW。它还通过在输出的串行输出（PISO）中的输入和平行于输入和平行于输出时使用串行（SIPO）来减少83到35的I / O计数。最大吞吐量是2字节输出/循环。 FPGA（Vertex-2Pro）实现以140 MHz的最大频率运行。可以轻松扩展架构以产生2-D小波变换。

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