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首页> 外文期刊>Analog Integrated Circuits and Signal Processing >A 1.0 V, 9.84fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications
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A 1.0 V, 9.84fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications

机译：1.0 V，9.84FJ / C-S FOM可重新配置的混合SAR-SIGMA DERTA ADC，用于信号处理应用

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摘要

In this paper, a novel, low power, 16-bit, 9.84fJ/conv-step FOM, reconfigurable, hybrid SAR-sigma delta ADC is presented. The ADC has been designed and implemented with two stages of programmable 4-bit SAR ADC followed by an 8-bit first order incremental sigma delta ADC. The resolution (which is reconfigurable), power and performance are controlled statically to get 12-bit, 14-bit, 16-bit operation. To minimize the power consumption, opamp turnoff technique is implemented between the stages. Mathematical modeling of the design is carried out using MATLAB SIMULINK. The ADC is fabricated in global foundries 180nm CMOS process and results presented are those actually measured. In terms of performance, the IC has a differential non-linearity of +/- 0.25 LSB, integral non-linearity of +/- 0.51 LSB, signal-to-noise distortion ratio of 91.1 dB and spurious-free dynamic range of 99.4dB. The Walden and Schreier figures of merit (FOMW and FOMS) at 1.6MHz sampling frequency are 9.84fJ/conversion-step and 183.6 dB respectively. Power consumption is measured to be 478 mu W @ 1.0V supply voltage and the total core area is found to be 0.15mm(2).
机译：本文提出了一种新颖的，低功耗，16位，9.84FJ / CONV-Step FOM，可重新配置的混合SAR-SIGMA DERTA ADC。 ADC已经设计和实现，具有两个可编程4位SAR ADC的阶段，然后是8位第一订单增量Sigma Delta ADC。分辨率（可重新配置），电源和性能在静态控制以获得12位，14位，16位操作。为了最小化功耗，在阶段之间实现了开放式岔路技术。使用Matlab Simulink进行设计的数学建模。 ADC在全球铸造厂制造中制造180nm CMOS工艺，并且呈现的结果是实际测量的结果。在性能方面，IC具有+/- 0.25 LSB的差分非线性，+/- 0.51 LSB的积分非线性，信号 - 噪声失真率为91.1dB，无杂散的动态范围为99.4dB 。瓦尔登和施莱尔的优点（FOMW和FOM）的数据分别为1.6MHz采样频率为9.84FJ /转换步骤和183.6 dB。测量功耗为478 mu W @ 1.0V电源电压，并且总芯区域为0.15mm（2）。

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