A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

Zhou Zhijun; Warr Paul

首页> 外文期刊>Analog Integrated Circuits and Signal Processing >A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

【24h】

A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

机译：分割布局保护技术，用于减轻集成电阻的寄生电容

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.

机译：在集成电路设计中，与实现电阻器相关的寄生电容可以限制某些应用的电路性能，例如模拟到数字转换器。在本文中，引入了分割保护布局技术，其提供了集成电阻器的寄生电容的绕。在扩散和多晶硅集成电阻上证明了分割保护技术。

著录项

来源
《Analog Integrated Circuits and Signal Processing》 |2017年第2期|共7页
作者
Zhou Zhijun; Warr Paul;
展开▼
作者单位

Univ Bristol Dept Elect &

Elect Engn Merchant Venturers Bldg Woodland Rd Bristol BS8 1UB Avon England;

Univ Bristol Dept Elect &

Elect Engn Merchant Venturers Bldg Woodland Rd Bristol BS8 1UB Avon England;

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类半导体集成电路（固体电路）;
关键词
CMOS; Integrated resistor; Segmented layout guarding; Parasitic capacitance;

机译：CMOS;集成电阻;分段布局保护;寄生电容;

相似文献

外文文献
中文文献
专利

1. A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors [J] . Zhou Zhijun, Warr Paul Analog Integrated Circuits and Signal Processing . 2017,第2期

机译：分割布局保护技术，用于减轻集成电阻的寄生电容
2. Parasitic capacitance effects of planar resistors [J] . Demurie S.N., De Mey G. IEEE Transactions on Components, Hybrids, and Manufacturing Technology . 1989,第3期

机译：平面电阻器的寄生电容效应
3. A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs [J] . Yeh K.-L., Guo J.-C. Electron Devices, IEEE Transactions on . 2011,第9期

机译：纳米级多指MOSFET布局依赖寄生电容分析和有效迁移率提取的新方法
4. Modeling and mitigation techniques of the magnetic integrated structures parasitic capacitance [C] . Racasan Adina Nicoleta, Pacurar Claudia, Munteanu Calin, 2012 47th International Universities Power Engineering Conference. . 2012

机译：磁性集成结构寄生电容的建模和缓解技术
5. Estimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuits. [D] . Sen, Padmanava. 2007

机译：基于硅的毫米波集成电路的布局寄生效应的估计和优化。
6. Device closure of diverse layout of multi-hole secundum atrial septal defect: different techniques and long-term follow-up [O] . Zeeshan Farhaj, Li Hongxin, Guo Wenbin, 2019

机译：闭孔多发性房间隔缺损布局的器械闭合：不同的技术和长期的随访
7. A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors [O] . Zhou Zhijun, Warr Paul 2017

机译：一种分段布局保护技术，可减轻集成电阻器的寄生电容
8. Numerical Technique for Removing Residual Gate-Source Capacitances When Extracting Parasitic Inductance for GaN High Electron Mobility Transistors (HEMTs) [R] . Huebschman, B., Shah, P. B. 2011

机译：在提取GaN高电子迁移率晶体管（HEmT）的寄生电感时去除残余栅源电容的数值技术

A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

摘要

著录项

相似文献

相关主题

期刊订阅