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Memristor-based approximate matrix multiplier

机译：基于Memristor的近似矩阵乘法器

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摘要

The parallel structure of matrix multipliers makes them fascinating candidates to benefit from memristors' high density architecture. This paper first explains a memristor-based analog vector-matrix multiplier suitable for approximate computing. According to the existence of fast and efficient converters, namely, DACs and ADCs, in the field of approximate computing and the programmability of memristors, the presented vector-matrix multiplier is combined with digital circuits which it leads to a matrix-matrix multiplier as an extension. In this work, opamps' characteristics such as power and speed, distribution of matrix elements, and memristors' faults have been considered and their effects on performance, accuracy, and efficiency of the proposed multiplier have been analyzed. Also, a new structure for handling negative numbers has been proposed. All the circuits have been simulated using "Ngspice mixed-signal circuit simulator'' in C?? programming environment. The simulation results revealed that the multiplier's analog core brought gains in terms of performance and energy when acceptable ranges of inaccuracies in results could be tolerated.
机译：矩阵乘法器的并行结构使得它们令人欣赏候选者，以受益于存储器的高密度架构。本文首先介绍了一种适用于近似计算的基于存储器的模拟矢量矩阵乘法器。根据存在快速高效的转换器，即DAC和ADC，在近似计算领域和存储器的可编程性，所示的矢量 - 矩阵乘法器与数字电路组合，其导致矩阵矩阵乘法器作为延期。在这项工作中，已经考虑了诸如电源和速度，矩阵元件的电源和速度，分布和存储器故障的特性，并且已经分析了所提出的乘数的性能，准确性和效率的影响。此外，已经提出了一种用于处理负数的新结构。所有电路都是在C ??编程环境中使用“NGSpice混合信号电路模拟器”模拟的。模拟结果表明，乘数的模拟核心在能够容忍上可接受的不准确范围的性能和能量方面带来了增益。

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