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首页> 外文期刊>Analog Integrated Circuits and Signal Processing >Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications
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Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

机译：用于DVFS应用的全数字快速瞬态锁相数字LDO-MDLL

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摘要

This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (F-REF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm(2). At the typical V-IN = 1.2 V and F-REF = 37.4 MHz, the regulated range of voltage was measured to be 0.56-1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than -116 and -104 dBc/Hz, respectively, both at 1 MHz offset.
机译：本文介绍了嵌入基于频率的频率参考（F-REF）的全数字低压丢失调节器（DLDO）的乘积延迟锁定环（MDLL），该乘积数字低压稳压器（DLDO）在驾驶数字负载电路时越优于传统的动态电压和频率缩放电路按下近阈值电压电平。我们还提出了一种前馈加速度（FFA）技术，该技术仅在瞬态期间动态激活，以减小由负载电流步骤引起的瞬态响应时间和电压下垂。所提出的DLDO嵌入式MDLL在40nm CMOS工艺中制造，占据0.02mm（2）的有源区。在典型的V-In = 1.2 V和F-REF = 37.4MHz，测量电压的调节范围为0.56-1.16 V，而频率从0.411缩放到2.35GHz。利用所提出的FFA技术，与正常环操作期间的值相比，负载瞬态响应和电压下降分别减少了61.5和35％。另外，在0.411和2.35GHz的测量阶段噪声分别在1MHz偏移量下分别小于-116和-104dBC / Hz。

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