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Low leakage and high CMRR CMOS differential amplifier for biomedical application

机译：用于生物医学应用的低泄漏和高CMRR CMOS差分放大器

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摘要

A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from V-DD to V-OUT or from V-SS to V-OUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn't reach from V-DD to V-SS directly i.e. the driving power of the circuit couldn't be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.
机译：探索了一种新颖，称职，轻松的低泄漏CMOS差分放大器，具有最小变形和适当的电力利用。所提出的电路还可以代表用于便携式生物医学信号采集系统的CMOS模拟前端（AFE）电路。所提出的电路旨在提供从V-DD到V形或V-SS到V-OUT的电源的意图。所提出的电路具有高CMRR。这意味着共模电压增益最小，差分模式电压增益很高。该电路以这样的方式设计，即电源不能直接从V-DD到V-SSS。电路的驱动功率不能短路。由此，所提出的电路表现得像完美的差分放大器。 CMOS逻辑的能力和推测性组合与NMOS晶体管的栅极端子交叉耦合，以提供所提出的差分放大器电路的更好功能。所提出的电路具有独特组合的MOS组合提供了更好的性能参数。由于利用改进的MOS结构具有上拉和下拉堆叠晶体管，差分放大器的增益因子增加到5 dB，与其他差分放大器电路相比，漏功率耗散降低至49％。提出的CMOS基差分放大器以45nm CMOS技术进行优化。已经使用Cadence模拟Virtuoso幽灵模拟器进行了模拟。已经通过所提出的电路进行泄漏功率和效率的分析来进行实验实施。

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