Two-step V-cm-based MS switching method with dual-capacitive arrays for SAR ADCs

Huang Jun; Wu Jianhui; Wu Aidong

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Two-step V-cm-based MS switching method with dual-capacitive arrays for SAR ADCs

机译：基于两步V-CM的MS切换方法，具有用于SAR ADC的双电容阵列

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摘要

An ultra-low-power two-step merge and split (MS) switching method for a dual-capacitive arrays (DCAs) successive approximation register analogue-to-digital converter is presented. This method only requires two reference levels, i.e. Gnd and V-cm (V-cm = 1/2V(ref)). Compared with the conventional method, the proposed method achieves 99.89 and 80.96% reduction in average switching energy and capacitors, respectively, meanwhile maintaining good linearity. In addition, it barely consumes reset energy and keeps common-mode voltage of DCAs almost constant.

机译：提出了用于双电容阵列（DCAS）连续近似寄存器模拟到数字转换器的超低功耗两步合并和分割（MS）切换方法。该方法仅需要两个参考电平，即GND和V-CM（V-CM = 1 / 2V（REF））。与常规方法相比，该方法分别达到平均切换能量和电容器的降低99.89和80.96％，同时保持良好的线性度。此外，它几乎没有消耗复位能量，并保持DCA的共模电压几乎恒定。

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《Analog Integrated Circuits and Signal Processing》 |2018年第1期|共6页
作者
Huang Jun; Wu Jianhui; Wu Aidong;
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作者单位

Southeast Univ Natl ASIC Res Ctr Nanjing 210096 Jiangsu Peoples R China;

Southeast Univ Natl ASIC Res Ctr Nanjing 210096 Jiangsu Peoples R China;

Southeast Univ Natl ASIC Res Ctr Nanjing 210096 Jiangsu Peoples R China;

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原文格式 PDF
正文语种 eng
中图分类半导体集成电路（固体电路）;
关键词
SAR ADC; Switching method; Two-step; V-cm-based; Linearity; Ultra-low-power;

机译：SAR ADC;切换方法;两步;基于V-CM;线性;超低功率;

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专利

1. Two-step V-cm-based MS switching method with dual-capacitive arrays for SAR ADCs [J] . Huang Jun, Wu Jianhui, Wu Aidong Analog Integrated Circuits and Signal Processing . 2018,第1期

机译：基于两步V-CM的MS切换方法，具有用于SAR ADC的双电容阵列
2. Energy-efficient charge-recovery switching scheme for dual-capacitive arrays SAR ADC [J] . Li Y., Zhang Z., Lian Y. Electronics Letters . 2013,第5期

机译：双电容阵列SAR ADC的高能效电荷恢复开关方案
3. A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS [J] . Yung-Hui Chung, Chia-Wei Yen, Meng-Hsuan Wu Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2016,第11期

机译：具有110nm CMOS的两步决策DAC开关的24μW12位1-MS / s SAR ADC
4. A 24#x03BC;W 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching [C] . Chung Yung-Hui, Wu Meng-Hsuan, Li Hung-Sung IEEE Custom Integrated Circuits Conference . 2013

机译：具有两步判决DAC开关的24μW12b 1MS / s 68.3dB SNDR SAR ADC
5. A 200MS/s 12-bit subranging SAR ADC [D] . Elies, Brian. 2015

机译：一个200ms / s 12位分级SAR ADC
6. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor [O] . Fang Tang, Amine Bermak, Abbes Amira, -1

机译：具有CMOS图像传感器误差校正功能的两步单斜率/ SAR ADC
7. Two-step switching scheme for SAR ADC with high energy efficiency [O] . Chenggao Zhang, Shubin Liu, Zhangming Zhu 2018

机译：具有高能量效率的SAR ADC的两步切换方案

Two-step V-cm-based MS switching method with dual-capacitive arrays for SAR ADCs

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