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首页> 外文期刊>International Journal of Applied Engineering Research >Design and Implementation of Modified Sequential Parallel RNS Forward Converters
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Design and Implementation of Modified Sequential Parallel RNS Forward Converters

机译：修改顺序并行RNS前进转换器的设计与实现

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The Residue Number System (RNS) is suitable for DSP architectures because of its ability to perform fast carry-free arithmetic. However, this advantage is over-shadowed by the complexity involved in the conversion of numbers between binary to RNS representations and have prevented the wide-spread use of RNS. Converting a number from a binary representation to its RNS equivalent is known as forward conversion while the inverse operation is called reverse conversion. Even though reverse conversion is generally more complex, forward conversion for arbitrary modulo sets is not simpler. However, forward conversion for arbitrary modulo sets is memory intensive. There are three main approaches for forward conversion. The first approach involves pre-computing all possible values that the conversion requires and storing these values in memory. The second approach involves using efficient arithmetic units called combinational logic along with memory (LUT). In both cases, the memory size requirement increases as the dynamic range increases. The third approach is memory less in that it involves only combinatorial logic in the design. In this thesis we proposed to four different architectures for second approach which uses combinational logic along with memory (LUTs). The first architecture is purely sequential conversion in the second architecture is combination of sequential and parallel. The third architecture is the modified version of second architecture and fourth architecture is purely parallel. Forward converter architecture is designed and implemented to reduce the area, speed. Verilog HDL is used for coding and implementation of different architectures has been done on XILINX VERTEX 5XC5VLX110T-2FF1136 OPEN SPARC board. It is been identified that modified sequential/parallel approach has better performance in speed and area when compared with existing architectures.
机译：残留号系统（RNS）适用于DSP架构，因为它能够进行快速无携带算术。然而，这种优势通过在二进制到RN表示之间的数字转换的复杂性而过度遮蔽，并且已经阻止了RNS的广泛使用。将来自二进制表示的数字从二进制表示转换为其RNS等效物是正向转换，而逆操作被称为反向转换。即使反向转换通常更复杂，对于任意模组的前向转换也不简单。但是，任意模具集的正向转换是内存密集型。前进转换有三种主要方法。第一种方法涉及预先计算转换所需的所有可能值并将这些值存储在内存中。第二种方法涉及使用称为组合逻辑的有效算术单元以及存储器（LUT）。在这两种情况下，随着动态范围的增加，内存大小要求增加。第三种方法是内存较少的，因为它涉及设计中的组合逻辑。在本文中，我们提出了四种不同的架构，用于第二种方法，它使用组合逻辑以及内存（LUT）。第一架构在第二架构中纯粹是顺序转换，是顺序和平行的组合。第三架构是第二架构的修改版本，第四架构纯粹并行。正向转换器架构设计并实现以减小该区域，速度。 Verilog HDL用于编码和实现不同架构的在Xilinx Vertex 5xC5VLX110T-2FF1136 Open Sparc Board上完成了不同的架构。已识别出修改的顺序/并行方法在与现有架构相比时具有更好的速度和区域性能。

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