A 5 GHz 8 × 8-Bit Multiplier Using Wave Component Sampling Method

Refik Sever; Murat Askar

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A 5 GHz 8 × 8-Bit Multiplier Using Wave Component Sampling Method

机译：使用波分量采样方法的5 GHz 8×8位乘法器

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摘要

A 0.18 μm 8 × 8 bit CSA multiplier with an operating frequency of 5 GHz at typical operating conditions (1.8 V supply and 27℃ temperature) is presented. This multiplier is designed by using Wave Component Sampling Method. In this method, only some of the components of the propagating data waves are sampled. Multiplier is full pipelined, i.e., a register stage is used after every logical operation. Comparing with the mesochronous pipelining method, the total number of latches is decreased by 45% and the overall power consumption of the multiplier is reduced by 18.4%.

机译：给出了在典型工作条件（1.8 V电源和27℃温度）下工作频率为5 GHz的0.18μm8×8位CSA乘法器。该乘数是通过使用波分量采样方法设计的。在这种方法中，仅对传播数据波的某些分量进行采样。乘法器是全流水线的，即在每次逻辑运算后都使用寄存器级。与同步流水线方法相比，锁存器总数减少了45％，乘法器的总功耗减少了18.4％。

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《Advanced Science Letters》 |2013年第5期|共4页
作者
Refik Sever; Murat Askar;
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原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Wave Pipelining; Multiplier; VLSI;

机译：波流水线;乘法器;VLSI;

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1. A 5 GHz 8 × 8-Bit Multiplier Using Wave Component Sampling Method [J] . Refik Sever, Murat Askar Advanced Science Letters . 2013,第5期

机译：使用波分量采样方法的5 GHz 8×8位乘法器
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3. Interconnections Between Multiplier Methods and Window Methods in Generalized Sampling [J] . Gerhard Schmeisser Sampling theory in signal and image processing . 2010,第1a3期

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4. Live Demo: An 88fJ / 40 MHz 0.4V – 0.61pJ / 1GHz 0.9V Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI [C] . Ramiro Taco, Itamar Levi, Marco Lanuzza, IEEE International Symposium on Circuits and Systems . 2019

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8. Progress Towards the Realization of MMIC Technology at Submillimeter Wavelengths: A Frequency Multiplier to 320 GHz [R] . Bruston, J., Smith, R., Martin, S., 1998

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A 5 GHz 8 × 8-Bit Multiplier Using Wave Component Sampling Method

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