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首页> 外文期刊>Silicon >Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications
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Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

机译：考虑CMOS低功耗应用的源/漏耗竭效应的双栅堆叠氧化物连接晶体管的分析模型

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摘要

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO(2)stacked oxide structure. The model is solved by Poisson's equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis.
机译：本文提出了一种二维分析模型，用于双栅极连接晶体管，具有SiO2 / HFO（2）堆叠氧化物结构。该模型由泊松等式使用可变分离方法来解决。该建议的模型提供了用于静电电位分布，阈值电压和漏极电流的分析表达，其耗尽区域在源极/漏极侧的效果。此外，潜在和漏极电流模型用于评估所提出的装置的短沟道效应（SCES）。通过不同可能的通道长度，硅厚度，等效氧化物厚度和耗尽长度变化来分析电特性和SCE。通过与Sentarus TCAD模拟器结果进行验证，验证了开发的模型结果。此外，还研究了所提出的装置，用于通过电压传递特性，瞬态分析和AC小信号分析来研究CMOS逆变器电路的数字电路性能。

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