Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

REFKA GHODHBANE; TAOUFIK SAIDANI; LAYLA HORRIGUE; MOHAMED ATRI

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Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

机译：图像压缩的平行因果架构的分析和VLSI高速

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Embedded block coding with optimized truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. With the augmentation in multimedia technology, demand for high speed real time image compression system has also increased. JPEG2000 is a relatively new image compression standard which builds and improves on its predecessor JPEG. In Jpeg 2000 the embedded Block Coding with Optimal Truncation (EBCOT) is the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. This paper proposes a Parallel Bit Plane Coding (BPC) architecture in which three coding passes operate in parallel and are allowed to progress independently.

机译：具有优化截断的嵌入式块编码（EBCOT）是数字电影（DC）分配系统的关键算法。虽然存在几种高速EBCOT架构，但都无法满足DC规范。随着多媒体技术的增强，对高速实时图像压缩系统的需求也增加了。 JPEG2000是一种相对较新的图像压缩标准，在其前身JPEG上构建和改进。在JPEG 2000中，具有最佳截断（EBCOT）的嵌入式块编码是计算JPEG 2000图像压缩标准的压缩过程中非常硬部分的最重要元素。本文提出了一种并行比特平面编码（BPC）架构，其中三个编码通过并联操作，并且允许独立进展。

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来源
《WSEAS Transactions on Signal Processing》 |2017年第1期|共7页
作者
REFKA GHODHBANE; TAOUFIK SAIDANI; LAYLA HORRIGUE; MOHAMED ATRI;
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作者单位

Faculty of Computing and Information Technology Northern Border University;

Faculty of Computing and Information Technology Northern Border University;

Electronics and Micro-Electronics Laboratory Faculty of Sciences Monastir University;

Faculty of Computing and Information Technology Northern Border University;

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原文格式 PDF
正文语种 eng
中图分类声学;
关键词
EBCOT; JPEG2000; VHDL; FPGA; VLSI;

机译：EBCOT;JPEG2000;VHDL;FPGA;VLSI;

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专利

1. Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression [J] . REFKA GHODHBANE, TAOUFIK SAIDANI, LAYLA HORRIGUE, WSEAS Transactions on Signal Processing . 2017,第Pta1期

机译：图像压缩的平行因果架构的分析和VLSI高速
2. A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000 [J] . Li Y., Bayoumi M. IEEE Transactions on Circuits and Systems for Video Technology . 2006,第9期

机译：JPEG 2000的EBCOT的三级并行高速低功耗架构
3. High speed VLSI architectures for DWT in biometric image compression: A study [J] . N. Vijaya Bala, Dr. R. Shanmughalakshmi Procedia Computer Science . 2010,第1期

机译：用于生物特征图像压缩的DWT的高速VLSI架构：一项研究
4. THREE-LEVEL PARALLEL HIGH SPEED ARCHITECTURE FOR EBCOT IN JPEG2000 [C] . Yijun Li, Magdy Bayoumi IEEE International Conference on Acoustics, Speech, and Signal Processing . 2005

机译：JPEG2000中ebcot三级并行高速架构
5. A VLSI architecture for lifting-based wavelet packet transform in fingerprint image compression. [D] . Zhu, Tao. 2003

机译：指纹图像压缩中基于提升的小波包变换的VLSI架构。
6. Biophysically interpretable recurrent neural network for functional magnetic resonance imaging analysis and sparsity based causal architecture discovery [O] . Yuan Wang, Yao Wang, Yvonne W. Lui -1

机译：可进行生物物理学解释的递归神经网络用于功能磁共振成像分析和基于稀疏性的因果架构发现
7. High speed VLSI architectures for DWT in biometric image compression: A study [O] . Bala N. Vijaya, Shanmughalakshmi Dr. R. 2010

机译：用于生物特征图像压缩的DWT的高速VLSI架构：一项研究
8. A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology [R] . Fang, W. C., Lin, T. H. 1999

机译：用于sOI CmOs技术的高速图像数据压缩的低功耗VLsI神经处理器设计

Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

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