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首页> 外文期刊>WSEAS Transactions on Circuits and Systems >VLSI Implementation of Lattice Wave Digital Filters for Increased Sampling Rate Using Three Port Parallel Adaptors
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VLSI Implementation of Lattice Wave Digital Filters for Increased Sampling Rate Using Three Port Parallel Adaptors

机译：VLSI使用三个端口并联适配器的采样率提高采样率的VLSI实现

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摘要

The second-order all-pass section is the main building block of the lattice wave digital filter (WDFs). The all-pass sections are conventionally realized using two port adaptors. In this paper, second-order all-pass sections are replaced with three port parallel adaptors. These adaptors, implemented with canonic signed digit coefficients are proposed to increase maximal sampling frequency of lattice WDFs. The proposed implementation of three port parallel adaptors reduces the latency of the critical loop by, reducing the components (adders and multipliers). Further increase in maximal sampling frequency is obtained by integrating these three port parallel adaptors using carry propagation adders (CPA) designed with low power and high performance 1-bit full adders, registers as delay elements and binary multipliers. Here, multipliers are implemented using a network of shifts and adders (or subtractors). An example of a filte implementation where the proposed approaches are applied, is presented. In this example multiple-constant multiplication technique is applied to reduce the number of adders in the implementation of multipliers. The sections are integrated using Design Architect and simulated using Eldonet tools of Mentor Graphics V2008 and tested by applying number of input vectors. The results are compared with the conventional second-order all-pass sections. The comparison shows the increase in maximal sampling frequency by approximately 46% at the cost of about 13%increase in area.
机译：二阶All-Pass部分是格子波数字滤波器（WDFS）的主构造块。全传递部分通常使用两个端口适配器实现。在本文中，二阶全通段被三个端口并联适配器替换。用Canonic签名的数字系数实现的这些适配器以增加格子WDF的最大采样频率。所提出的三个端口并行适配器的实施降低了临界环路的延迟，减少了组件（加法器和乘法器）。通过将这些三个端口并联适配器（CPA）与设计为低功率和高性能1位全加入器（作为延迟元件和二进制乘法器为设计的携带传播添加剂（CPA）集成了这三个端口并联适配器而进一步增加了最大采样频率。这里，使用班次和加法器（或减法器）网络实现乘法器。介绍了应用所提出的方法的FILTE实现的示例。在该示例中，应用多常数乘法技术以减少乘法器实现中的加法器的数量。这些部分使用设计架构师集成，并使用Mentor Graphics V2008的EldOnet工具模拟，并通过应用输入向量的数量来测试。将结果与传统的二阶全通段进行比较。比较表明，最大采样频率的增加约为46％，成本约为13％。

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