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首页> 外文期刊>Journal of Low Power Electronics >Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond
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Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond

机译：为5纳米技术及以外的互连技术和设计共同优化

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CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. Increasing resistance of the interconnectand increasing device parasitics limit the gains from any device improvement because of voltage drops. In this paper we will address various mitigation approaches in both technology and design to enable PPA (Performance-Power-Area) scaling for the 5 nm technology node and beyond. Technologysolutions include low-k device spacers, wrap-around contact for improved device parasitics and non-Cu based interconnects for improved interconnect resistance. Design solutions focus on improving cell drive by optimally sizing the device and focus on key layout constructs for loweringthe impact of parasitics while enabling much more compact standard cells. Finally, we point out challenges of increasing power density by scaling and tightening defectivity control, particularly in 3D integration.
机译：到目前为止，CMOS缩放到目前为止，通过延迟，电源和区域的并行改进，通过延迟，电源和区域进行同时启用同时系统吞吐量缩放。 CMOS缩放随着互连的限制和增加晶片成本而变得更加困难。由于电压降，互连的增加的互连阻力增加了从任何设备改进的增益。在本文中，我们将解决技术和设计中的各种缓解方法，以使5 NM技术节点及更远的PPA（性能 - 电源区）缩放。技术olluer包括低 K器件间隔物，包裹围绕改进的装置寄生剂和基于非Cu基于互连电阻的互连。设计解决方案专注于通过最佳地尺寸尺寸尺寸改善细胞驱动，并专注于关键布局构造，以降低寄生件的影响，同时实现更紧凑的标准电池。最后，我们通过缩放和收紧缺陷控制来指出增加功率密度的挑战，特别是在3D集成中。

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