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A Retrospective View on the Technology Evolution to Support Low Power Mobile Application

机译:技术演化的回顾视图支持低功率移动应用

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In the pursuit of technology scaling, the semiconductor industry has faced steep challenges in meeting low power targets for mobile application. While the voltage scaling has been slowed down beyond 45 nm technologies, industry has managed to enable alternate means for continued scalingof power delay product over technology generations. These include the evolution of process level improvements and device structure engineering as well as the circuit and architecture level innovation. In this paper, we review key technology elements that have contributed to the continued scalingof power for mobile applications while meeting the ever growing demands for performance (throughput). We will discuss the impact of process elements such as high-K metal gate, low-K spacer, SiGe stress, etc. as well as the device structure engineering from a planar device toFinFET and FDSOI to the overall device electrostatics and their scalability. We will also discuss the effect of design technology co-optimization (DTCO) in achieving PPA (power performance and area) scaling targets in advanced technology nodes. Further, we will review fundamental design IPlike SRAM (static random access memory) in advanced technology nodes.
机译:在追求技术缩放中,半导体行业在满足移动应用的低功率目标方面面临着急剧挑战。虽然电压缩放已经减慢超过45纳米技术,但行业已经设法启用较持续的缩放电源延迟产品的替代手段。其中包括工艺级改进和器件结构工程的演变以及电路和建筑级别创新。在本文中,我们审查了关键技术元素,这些元素有助于持续的移动应用程序的电力,同时满足对绩效的不断增长的需求(吞吐量)。我们将讨论过程元素,如高 k金属栅极,低 k间隔,SiGe应力等的影响以及从平面装置Tofinfet和FDSOI到整个装置的器件结构工程静电和可扩展性。我们还将讨论设计技术协同优化(DTCO)在高级技术节点中实现PPA(功率性能和面积)缩放目标的影响。此外,我们将在高级技术节点中审查基本设计IPlike SRAM(静态随机存取存储器)。

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