Low Power and Energy Efficient Asynchronous Design

Peter A. Beerel; Marly E. Roncken

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Low Power and Energy Efficient Asynchronous Design

机译：低功耗和节能异步设计

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This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip.

机译：本文调查最有前途的低功耗和节能异步设计技术，可通过同步对应物导致具有实质优势。我们的讨论涵盖了各种设计，应用程序和域中的异步和同步实现之间的宏观体系结构，微架构和电路级别差异，包括微处理器，应用特定设计和芯片上的网络。

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来源
《Journal of Low Power Electronics》 |2007年第3期|共20页
作者
Peter A. Beerel; Marly E. Roncken;
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正文语种 eng
中图分类无线电电子学、电信技术;
关键词
Asynchronous Design; Low-Power; Energy-Efficiency; Latch-Based Design; Dynamic Voltage Scaling; Subthreshold Design; GALS; Asynchronous NoC; Perfect Clock Gating;

机译：异步设计;低功耗;能效;基于闩锁的设计;动态电压缩放;亚阈值设计;GALS;异步NOC;完美的时钟门控;

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1. Low Power and Energy Efficient Asynchronous Design [J] . Peter A. Beerel, Marly E. Roncken Journal of Low Power Electronics . 2007,第3期

机译：低功耗和节能异步设计
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3. Asynchronous DSP for low-power energy-efficient embedded systems [J] . Yiqiong Shi, Bah-Hwee Gwee, Joseph Chang Microprocessors and microsystems . 2011,第3期

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Low Power and Energy Efficient Asynchronous Design

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