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首页> 外文期刊>Journal of Low Power Electronics >Differential Cascode Adiabatic Logic Structure for Low Power
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Differential Cascode Adiabatic Logic Structure for Low Power

机译：低功率的差分共源级码绝热逻辑结构

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摘要

This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies.
机译：本文介绍了差分级联预解析绝热逻辑（DCPAL），可以更大的功能，更大的风扇和高能量效率运行。它是由四个相位动力时钟为绝热管道运行的二极管和双轨逻辑。差分共级结构和数量较少数量的晶体管，互补输入的预解析特征较少，实现了延迟的降低，开关电容的显着下降，实现了功率效率，更好的硅面积效率，降低泄漏路径和无故障输出减少开关瞬变。证明了针对静态CMOS等效和更好的速度性能的能量效率和针对2N2P，2N2N2P，PFAL和IPGL等效电路的更好的速度性能。通过使用全定制电路设计采用的多比特加法器和乘法器电路的后布局模拟，DCPAL在100 MHz功率时钟频率下实现了20.85的绝热增益值，以500 MHz的9.88抵抗静态CMOS等效的8位Wallace树乘法器电路。在500 MHz的优化的2N2N2P和PFAL 8位乘数电路下实现了50％和45％的节能，并且对这些电路的节能在更高的频率下进一步增强。

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