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A Framework to Compare Estimated and Measured Power Consumption on FPGAs

机译：用于比较FPGA上估计和测量功耗的框架

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In this paper, an extensive review of the available publications about comparing estimations versus measurements of power consumption in FPGA technology is carried out. This study reveals that the variety of experimental setups makes it difficult to elaborate solid studies departingfrom the results of different researchers using meta-analysis techniques. To mitigate this problem, we propose a procedure to standardize the setup of FPGA power estimation experiments. The goal is to make as close as possible power estimations and their corresponding actual on-chip measurements.The main idea is to use a fixed arrangement composed by a parameterized pattern generator block at the input, together with a set of interchangeable IP cores utilized as reference circuits. All the blocks are mapped together inside the FPGA sample, being the clock and reset lines the soleinput signals. Thus, both power estimation and actual measurements are performed to the whole system in identical conditions. In order to illustrate the method, the paper includes some examples of the proposed methodology for different cores. A set of 25 circuits have been tested in two FPGAfamilies, obtaining relative errors in power estimation between –61.5% and 9.2%.
机译：在本文中，进行了对比较估计的可用出版物的广泛审查与FPGA技术中的功耗测量。本研究表明，各种实验装置使得难以使用Meta分析技术从不同研究人员脱离的实体研究。为缓解此问题，我们提出了一种规范FPGA功率估计实验的设置。目标是尽可能接近电力估计和它们相应的实际片上测量。主要思想是使用由输入的参数化模式生成器块组成的固定装置，以及一组可互换的IP核心使用参考电路。所有块都在FPGA样本内部映射在一起，是时钟并重置索入信号。因此，在相同的条件下对整个系统执行功率估计和实际测量。为了说明该方法，本文包括针对不同核的提出方法的一些示例。在两个FPGaFamilies中测试了一组25个电路，从功率估计中获得的相对误差-61.5％和9.2％。

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