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首页> 外文期刊>Journal of Low Power Electronics >Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks
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Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

机译：考虑基于晶体管堆叠的局部变化，电压和温度可伸缩逻辑电池泄漏模型

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We propose a logic gate leakage model based on transistor stacks, which includes local transistor level process variation parameters along with global process variation parameters and supply and temperature. The stack models include both subthreshold as well as gate leakage and consider the input vector state. We examine cells from an industrial standard cell library and find that most cells can be modeled with simple stacks, which have a linear chain of transistors. However some gates like XOR, Majority or Muxes need complex stacks and we show how these can be modeled. Our experiments show that only 18 different stack models are needed to predict the leakage of all gates in this industrial library. Re-use of the same models for pass transistor logic circuits and multi-finger transistors is also demonstrated. We explicitly include voltage and temperature into the models to support joint estimation of power supply IR drops and leakage currents, as well as enable analysis for dynamic voltage scaling applications. We use artificial neural networks to create unified models which include global and local process variations, supply voltage in the range of V{sub}(DD)/2 - V{sub}(DD) and temperature in the range 0-100°C. These models are very useful for performing statistical leakage analysis of large circuits. Results from the ISCAS'85 benchmark circuits show that neural network based stack models can predict the PDF of leakage current of large circuits across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 7% when compared to SPICE. Further gate level validation has been done for both an industrial 130 nm and 45 nm PTM model files.
机译：我们提出了一种基于晶体管堆叠的逻辑栅极泄漏模型，其包括局部晶体管电平处理变化参数以及全局处理变化参数和供应和温度。堆叠模型包括亚阈值以及栅极泄漏，并考虑输入矢量状态。我们检查来自工业标准单元库的细胞，并发现大多数小区可以用简单的堆叠进行建模，其具有晶体管的线性链。然而，一些栅栏等XOR，大多数或MUXEE需要复杂的堆栈，我们展示了如何建模这些堆栈。我们的实验表明，只需要18种不同的堆叠模型来预测该工业图书馆中所有门的泄漏。还证明了用于传递晶体管逻辑电路和多指晶体管的相同型号的重新使用。我们明确地包括电压和温度进入模型，以支持电源IR滴和漏电流的联合估计，以及能够进行动态电压缩放应用的分析。我们使用人工神经网络来创建统一的模型，包括全局和局部处理变化，V {Sub}（DD）/ 2 - V {Sub}（DD）范围内的电源电压为0-100°C范围内的温度。 。这些模型对于对大电路进行统计泄漏分析非常有用。 ISCAS'85基准电路的结果表明，神经网络的堆栈模型可以在电源电压和温度上准确地预测大电路的漏电流的PDF，平均误差均为小于2％，标准偏差小于与香料相比，7％。为工业130nm和45 nm ptm模型文件进行了进一步的栅极级验证。

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