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首页> 外文期刊>Analog Integrated Circuits and Signal Processing >Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs
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Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs

机译：通过DG-MOSFET中的背栅偏置改善了阈值逻辑门中的可重构性和噪声容限

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摘要

We present a compact and error tolerant implementation of reconfigurable threshold logic gates (TLG) based on nanoscale DG-MOSFET transistors. The use of independently driven double-gate (IDDG) MOSFETs to build a TLG leads not only to fine-grain reconfigurability by way of voltage-adjustable threshold level (T), but also allows one to vary input weights (w_i) or reduce number of inputs (x_i), depending on the design preferences. Operation of the proposed TLG circuits is verified using UFDG SPICE model, and design trade-offs in terms of size, functionality and performance are also indicated. We show that IDDG MOSFETs lead to more efficient and compact TLG circuits that have better design latitude and noise immunity than the conventional counterparts, while also improving the overall reconfigurability. When the backgate dynamic threshold adjustment afforded by the ultrathin (<10 nm) DG-MOSFETs on SOI substrates is properly understood and utilized, similar to the floating-gate logic architectures, it can be effectively harnessed to create reconfigurability beyond T and can simplify TLG circuit design.
机译：我们提出了一种基于纳米级DG-MOSFET晶体管的可重构阈值逻辑门（TLG）的紧凑且容错的实现。使用独立驱动的双栅极（IDDG）MOSFET来构建TLG不仅可通过电压可调阈值水平（T）来实现细粒度的可重新配置，而且还允许人们改变输入权重（w_i）或减少数量输入（x_i）的数量，具体取决于设计偏好。使用UFDG SPICE模型验证了所建议的TLG电路的操作，并在尺寸，功能和性能方面进行了设计折衷。我们证明，IDDG MOSFET导致了更高效，更紧凑的TLG电路，与传统的同类产品相比，它们具有更好的设计纬度和抗噪性，同时还改善了整体可重构性。当正确理解并利用SOI衬底上超薄（<10 nm）DG-MOSFET提供的背栅动态阈值调整时，类似于浮栅逻辑架构，可以有效地利用它来创建超过T的可重构性并简化TLG电路设计。

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