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首页> 外文期刊>Physica Scripta: An International Journal for Experimental and Theoretical Physics >Unified compact model for junctionless multiple-gate FETs including source/drain extension regions
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Unified compact model for junctionless multiple-gate FETs including source/drain extension regions

机译：无连接多门FET的统一紧凑型号，包括源/排水延伸区

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摘要

This paper presents a unified compact model for a junctionless (JL) multiple-gate (MG) FET operating in the subthreshold region. A unified center potential model for double-gate, triple-gate, and quadruple-gate (QG) JL FETs is obtained using a quasi-3D scaling equation. The source/drain (S/D) extension regions are also modeled depending on the S/D extension length. The subthreshold current and subthreshold characteristics such as the subthreshold slope, threshold voltage, and drain-induced barrier lowering are analytically modeled for JL MG FETs. Comparison of the proposed models with numerical simulation results obtained using Sentaurus TCAD showed good accuracy, even for a very-short-channel QG device with a channel length of 10 nm. The proposed compact model can be used for low power circuit applications of JL MG FETs.
机译：本文提出了亚阈值区无结（JL）多栅（MG）FET的统一紧凑模型。利用准三维标度方程，得到了双栅、三栅和四栅（QG）JL FET的统一中心势模型。源/漏（S/D）扩展区域也根据S/D扩展长度进行建模。对JL MG FET的亚阈值电流和亚阈值特性，如亚阈值斜率、阈值电压和漏感势垒降低进行了分析建模。将提出的模型与使用Sentaurus TCAD获得的数值模拟结果进行比较，结果表明，即使对于通道长度为10 nm的非常短的QG器件，也具有良好的精度。所提出的紧凑模型可用于JL MG FET的低功耗电路应用。

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