Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

REFKA GHODHBANE; TAOUFIK SAIDANI; LAYLA HORRIGUE; MOHAMED ATRI

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Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

机译：图像压缩的平行因果架构的分析和VLSI高速

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Embedded block coding with optimized truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. With the augmentation in multimedia technology, demand for high speed real time image compression system has also increased. JPEG2000 is a relatively new image compression standard which builds and improves on its predecessor JPEG. In Jpeg 2000 the embedded Block Coding with Optimal Truncation (EBCOT) is the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. This paper proposes a Parallel Bit Plane Coding (BPC) architecture in which three coding passes operate in parallel and are allowed to progress independently.

机译：嵌入式优化截断块编码（EBCOT）是数字电影（DC）分发系统中的关键算法。尽管存在几种高速EBCOT架构，但它们都不能满足DC规范。随着多媒体技术的发展，人们对高速实时图像压缩系统的需求也越来越大。JPEG2000是一种相对较新的图像压缩标准，它是在其前身JPEG的基础上建立和改进的。在JPEG2000图像压缩标准中，嵌入的最佳截断块编码（EBCOT）是计算压缩过程中非常困难部分的最重要元素。本文提出了一种并行位平面编码（BPC）体系结构，其中三个编码过程并行运行，并允许独立进行。

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来源
《WSEAS Transactions on Signal Processing》 |2017年第1期|共7页
作者
REFKA GHODHBANE; TAOUFIK SAIDANI; LAYLA HORRIGUE; MOHAMED ATRI;
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作者单位

Faculty of Computing and Information Technology Northern Border University;

Faculty of Computing and Information Technology Northern Border University;

Electronics and Micro-Electronics Laboratory Faculty of Sciences Monastir University;

Faculty of Computing and Information Technology Northern Border University;

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原文格式 PDF
正文语种 eng
中图分类声学;
关键词
EBCOT; JPEG2000; VHDL; FPGA; VLSI;

机译：EBCOT;JPEG2000;VHDL;FPGA;VLSI;

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1. A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000 [J] . Liu Kai, Wu Chengke, Li Yunsong 电子科学学刊（英文版） . 2006,第001期
2. A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000 [J] . Liu, Kai, Wu, 电子科学学刊：英文版 . 2006,第001期
3. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT [J] . 电子科学学刊（英文版） . 2006,第002期
4. Deformation of the Zhangjiazhuang high-speed railway tunnel:an analysis of causal mechanisms using geomorphological surveys and D-InSAR monitoring [J] . MENG Xing-min, MA Jin-hui, ZHANG Yi, 山地科学学报（英文版） . 2021,第007期
5. Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression [J] . REFKA GHODHBANE, TAOUFIK SAIDANI, LAYLA HORRIGUE, WSEAS Transactions on Signal Processing . 2017,第Pta1期

机译：图像压缩的平行因果架构的分析和VLSI高速
6. A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000 [J] . Li Y., Bayoumi M. IEEE Transactions on Circuits and Systems for Video Technology . 2006,第9期

机译：JPEG 2000的EBCOT的三级并行高速低功耗架构
7. A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000 [J] . Li Y., Bayoumi M. IEEE Transactions on Circuits and Systems for Video Technology . 2006,第期

机译：JPEG 2000的EBCOT的三级并行高速低功耗架构
8. THREE-LEVEL PARALLEL HIGH SPEED ARCHITECTURE FOR EBCOT IN JPEG2000 [C] . Yijun Li, Magdy Bayoumi IEEE International Conference on Acoustics, Speech, and Signal Processing . 2005

机译：JPEG2000中ebcot三级并行高速架构
9. A VLSI architecture for lifting-based wavelet packet transform in fingerprint image compression. [D] . Zhu, Tao. 2003

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10. Biophysically interpretable recurrent neural network for functional magnetic resonance imaging analysis and sparsity based causal architecture discovery [O] . Yuan Wang, Yao Wang, Yvonne W. Lui -1

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11. High speed VLSI architectures for DWT in biometric image compression: A study [O] . Bala N. Vijaya, Shanmughalakshmi Dr. R. 2010

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12. A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology [R] . Fang, W. C., Lin, T. H. 1999

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Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

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