BLOCK SYNTHESIS OF COMBINATIONAL LOGIC IN APPLICATION-SPECIFIC VLSI CIRCUITS

P. N. Bibilo; N. A. Kirienko

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BLOCK SYNTHESIS OF COMBINATIONAL LOGIC IN APPLICATION-SPECIFIC VLSI CIRCUITS

机译：专用VLSI电路中组合逻辑的块综合

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摘要

The problem of synthesis in application-specific integrated circuits (ASIC) in the form of VLSI circuits for combinational logic in the form of an interrelated network of blocks, or programmable logic arrays (PLA), is considered. Realization of a block may be also achieved in the form of a network of library logic elements, or gate arrays (GA). Results of experimental investigations are presented.

机译：考虑了以用于集成电路的VLSI电路形式的专用集成电路（ASIC）中的合成问题，该逻辑形式为相互关联的块或可编程逻辑阵列（PLA）网络。块的实现也可以以库逻辑元件或门阵列（GA）的网络形式实现。介绍了实验研究的结果。

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《Automatic Control and Computer Sciences》 |2005年第2期|共7页
作者
P. N. Bibilo; N. A. Kirienko;
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原文格式 PDF
正文语种 eng
中图分类自动控制理论;
关键词
system of Boolean functions; disjunctive normal form; programmable logic array; library logic elements; very-large-scale integrated circuit;

机译：布尔函数系统;析取范式;可编程逻辑数组;库逻辑元素;超大规模集成电路;

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专利

1. BLOCK SYNTHESIS OF COMBINATIONAL LOGIC IN APPLICATION-SPECIFIC VLSI CIRCUITS [J] . P. N. Bibilo, N. A. Kirienko Automatic Control and Computer Sciences . 2005,第2期

机译：专用VLSI电路中组合逻辑的块综合
2. Application-Specific FPGA Using Heterogeneous Logic Blocks [J] . HUSAIN PARVEZ, ZIED MARRAKCHI, ALP KILIC, ACM transactions on reconfigurable technology and systems . 2011,第3期

机译：使用异构逻辑模块的专用FPGA
3. Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime [J] . Rana Ashwani K. International journal of numerical modelling . 2016,第3期

机译：设备电路共同设计，以减少纳米制度中VLSI逻辑电路中的栅极漏电流
4. Design of combinational logic digital circuits using a mixed logic synthesis method [C] . Balasubramanian P., Narayana M.R.L., Chinnadurai R. Emerging Technologies, 2005. Proceedings of the IEEE Symposium on . 2005

机译：使用混合逻辑综合方法设计组合逻辑数字电路
5. Empirical Genetic Algorithm Parameter Tuning Concerning the Synthesis of Combinational Logic Circuits. [D] . Ward, Joshua. 2017

机译：关于组合逻辑电路综合的经验遗传算法参数调整。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates [O] . Duarte Lopes de Oliveira, Orlando Verducci, Vitor Leandro Vieira Torres, 2018

机译：基于基础栅极的空约定逻辑综合QDI组合电路

BLOCK SYNTHESIS OF COMBINATIONAL LOGIC IN APPLICATION-SPECIFIC VLSI CIRCUITS

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