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Modeling Combo PR Generator for Stego Storage Self Test (SSST)

机译：用于隐身存储自测（SSST）的Combo PR生成器建模

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摘要

Steganography, a protected envelope for information systems is reaching new horizons at software as well as hardware level. Due to the number of benefits that result in using reconfigurable hardware like FPGA for stego system development, some attention is needed in performing the stego memory testing. While Self test methodologies adopted for memories require attention due to the extensive memory requirements, testing the secret carrier stego memory modules occupies the center stage due to its higher importance of data protection. Normally block RAMs inside FPGA can store the cover and stego images. With the hardware pseudorandom pattern generators, the memory testing can be done effectively. In this regard, the present work focuses on the implementation and analysis of various combined multiple LFSR based pseudorandom sequence generation schemes for Stego Memory self testing on Cyclone II EP2C20F484C7 FPGA. Analysis of the different schemes for their suitability to stego memory arena is an important objective of this work and also sequence distribution analysis has been carried out to verify the distribution of pseudorandom sequences for N clock cycles. The synthesis reports for all the four cases undertaken in this work have also been reported.
机译：隐写术是信息系统的一个受保护的信封，在软件和硬件方面都达到了新的视野。由于将诸如FPGA之类的可重新配置硬件用于隐身系统开发会带来许多好处，因此在进行隐身存储器测试时需要引起注意。尽管由于广泛的存储要求而需要注意用于存储器的自检方法，但是由于其对数据保护的重要性更高，因此测试秘密载体隐身存储模块占据了中心位置。通常，FPGA内部的Block RAM可以存储封面和隐秘图像。使用硬件伪随机码型发生器，可以有效地完成内存测试。在这方面，本工作着重于在Cyclone II EP2C20F484C7 FPGA上针对Stego Memory自检的各种基于多个LFSR的组合伪随机序列生成方案的实现和分析。分析不同方案对它们的隐身记忆空间的适用性是这项工作的重要目标，并且还进行了序列分布分析，以验证N个时钟周期的伪随机序列的分布。还报告了这项工作中所有四个案例的综合报告。

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