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Digital synchronous detector with a generator of a slowly

机译:具有同步发生器的数字同步检波器

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摘要

A synchronous detector based on a counter, memory device (RAM or ROM), and multiplicating digital-to-analog converter is described. At a ±25-V acceptable input signal, the output bias drift referred to the input is less than 30 μV, input bias suppression is 56 dB, and harmonic (the third and higher ones) suppression is no lower than 33 dB. The device can be used as a two-channel generator of arbitrarily shaped signals (from ultralow frequencies to 15 kHz).
机译:描述了一种基于计数器,存储设备(RAM或ROM)以及乘法数模转换器的同步检测器。在±25V可接受的输入信号下,相对于输入的输出偏置漂移小于30μV,输入偏置抑制为56 dB,谐波(三次或更高)的抑制不低于33 dB。该器件可用作任意形状信号的两通道发生器(从超低频到15 kHz)。

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