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Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA

机译:斯坦福大学电气工程系,美国斯坦福,加利福尼亚州94305

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摘要

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.
机译:由于设备和材料研究的紧密联系,电子历史上的创新​​成为可能。对低电压,低功耗和高性能的需求是低于50nm栅极长度CMOS器件工程设计的巨大挑战。已经证明了在5 nm沟道长度范围内的功能性CMOS器件。通过解决在栅极/沟道和衬底,栅极电介质以及源极和漏极工程中要解决的问题,对允许增加器件的可驱动性和降低功率的替代架构进行了审查。 HiK栅极电介质和金属栅极是考虑功耗和低电源电压管理的最具战略意义的选择。与CMOS逻辑竞争将非常困难,因为获得高性能需要低的串联电阻。通过引入新材料(Ge,金刚石/石墨碳,HiK等),基于Si的CMOS规模将超越ITRS,成为集成新的破坏性设备的未来片上系统平台。例如,将C金刚石与HiK结合在一起用于新型功能性埋入式绝缘子,将带来改善短通道效应并抑制自热的新方法。这将允许对Ion-Ioff权衡进行新的优化。低功耗,短通道效应以及高性能的控制将是未来的主要挑战。

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