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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth
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A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

机译:具有2.5 MHz信号带宽的14位连续时间Δ-Σ模数调制器

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摘要

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25μm CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.
机译:该文介绍了一种在2.5 V 0.25μm CMOS工艺中输出速率为5 MS/s的连续时间Δ-Σ A/D调制器。该调制器采用五阶单级双环路架构,允许近一个时钟周期量化器延迟。采用多位量化器提高分辨率,采用多位不归零DAC降低时钟抖动灵敏度。电容器调谐用于克服由于工艺变化引起的环路系数偏移。实现自校准以抑制电流导向DAC失配。该原型芯片的时钟频率为60 MHz,在12倍过采样比下实现了81 dB的峰值SNR和85 dB的动态范围。功耗为 50 mW。

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