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首页> 外文期刊>Engineering Fracture Mechanics >Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability
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Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

机译：亚微米级堆叠层的混合模式内聚区参数，可预测微电子器件的可靠性

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摘要

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today's high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers.
机译：随着微电子器件尺寸的不断减小以及单个集成电路（IC）上晶体管的数量超过十亿个，片上互连已成为处理，电气，热学和机械方面的挑战。当今的高性能IC具有片上线路后端（BEOL）层，该层由铜走线和过孔以及低k介电材料构成。这些层在晶体管附近的厚度在100nm的范围内，而在晶体管和焊料凸点附近的厚度在1000nm的范围内。在这样的BEOL叠层中，由于介电材料的低机械和粘合强度以及高的热诱导应力，开裂和/或分层是常见的失效模式。但是，没有可用的内聚区模型和参数来研究亚微米厚的微电子层中的此类界面裂纹。

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