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Differential signaling with a reduced number of signal paths

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Differential signaling is often used for digital chip-to-chip interconnects because it provides common-mode noise rejection. Unfortunately, differential signals generally require 2N signal paths to communicate N signals. In this paper, a method for differential signaling is described that requires as few as N+1 signal paths for N signals. Using this method, the signal values appear incrementally between neighboring matched signal paths. The technique, called incremental signaling, is similar to dicode (1 - D) partial response signaling except that the sequence is transmitted in parallel over a bus of wires rather than sequentially in time. Theoretical and simulated bit error rates are presented for several possible implementations of an encoder/transmitter and receiver/decoder for a digital data bus including peak detection and maximum likelihood sequence detection (MLSD). Peak detection uses N+l signal paths and results in a 3-dB performance degradation with respect to independent noise compared with fully differential signaling. The Viterbi algorithm for MLSD uses N+2 signal paths but provides only a 1.25dB improvement over peak detection due to correlated noise on the (1 - D)-coded sequence. Modified Viterbi algorithms that use N+2 signal paths are introduced to cancel the correlated noise sources, resulting in a bit error rate performance comparable with fully differential signaling.

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