A digital error-averaging technique for pipelined A/D conversion

P. Rombouts; L. Weyten

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A digital error-averaging technique for pipelined A/D conversion

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摘要

Capacitor mismatch is the main source of nonlinearity for pipelined analog-to-digital (A/D) converters. Here a digital error-averaging technique is presented to greatly reduce this effect. Compared to the conventional circuit, the new approachrequires only one extra digital addition. This allows a very simple and compact implementation. On the other hand, the conversion speed is halved because one conversion now requires two clock cycles instead of one. Therefore this technique is mostsuitable when moderately high speed combined with high resolution is required.

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《IEEE Transactions on Automatic Control》 |1998年第9期|1321-1323|共3页
作者
P. Rombouts; L. Weyten;
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正文语种英语
中图分类自动化系统;
关键词
Analog signal processing; Analog-to-digital conversion; Circuit techniques;

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A digital error-averaging technique for pipelined A/D conversion

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