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A memory/adder model based on single C_(60) molecular transistors

机译：基于单个C_（60）分子晶体管的存储器/加法器模型

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摘要

A recent proposal, in which 1-bit memory cells and simple logic gates such as NOT and NOR gates were based on C_(60) molecules in an electromechanical grid acting as transistors, is extended to larger architectures. In order to meet the requirements of standard digital circuit architectures, some modifications have to be made compared to the original model. For example, the number of transistors has to be increased from two to thirteen for a single NOR gate to guarantee balanced logical levels. In the scheme employed to achieve this in the current work, all two-input gates, namely OR, AND and XOR gates, can be easily constructed using the same concept. These gates are then used to design a 1-bit full-adder and a clocked D-latch, which are then combined with the earlier proposed 1-bit memory cell as the basic constituents of a memory/adder model. Clocked signal transmissions, corresponding to the read process of two 2-bit words from memory cells, their movement through registers and finally their addition and passing the output through another register, are simulated using the electrical circuit software SPICE. For the design of this memory/adder circuit, 464 single C_(60) transistors are used.
机译：最近的提议被扩展到更大的体系结构，其中1位存储单元以及简单的逻辑门（例如NOT和NOR门）基于机电栅中的C_（60）分子，该结构被用作晶体管。为了满足标准数字电路体系结构的要求，与原始模型相比，必须进行一些修改。例如，对于单个或非门，必须将晶体管的数量从两个增加到十三个，以保证平衡的逻辑电平。在当前工作中采用的实现此方案的方案中，可以使用相同的概念轻松构建所有两个输入门，即“或”，“与”和“异或”门。然后将这些门用于设计1位全加器和时钟控制D锁存器，然后将它们与较早提出的1位存储单元结合起来，作为存储/加法器模型的基本组成部分。使用电路软件SPICE模拟了时钟信号传输，该信号传输对应于从存储单元读取两个2位字的过程，它们在寄存器中的移动，最后是它们的加法运算以及通过另一个寄存器的输出传递。对于此存储器/加法器电路的设计，使用了464个单个C_（60）晶体管。

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