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Growth of two-dimensional arrays of silicon nanocrystals in thin SiO_2 layers by low pressure chemical vapour deposition and high temperature annealing/oxidation. Investigation of their charging properties

机译:通过低压化学气相沉积和高温退火/氧化在薄SiO_2层中生长硅纳米晶体的二维阵列。研究其充电特性

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摘要

Two-dimensional arrays of silicon nanocrystals embedded in ultrathin SiO_2 layers for application in silicon nanocrystal memories were fabricated by a three-step process: (a) growth of a tunnelling silicon oxide, (b) low pressure chemical vapour deposition (LPCVD) of a thin layer of amorphous silicon (alpha-Si), and (c) solid phase crystallization of the a-Si layer in a high temperature furnace under nitrogen flow, followed by thermal oxidation in the same furnace. Transmission electron microscopy (TEM) was used for the structural characterization of the three-layer structure and the determination of layer thicknesses and silicon nanocrystal size, while capacitance-voltage (C-V) and current-voltage (I-V) measurements were used to investigate the charging properties of the silicon nanocrystal layer. In an attempt to increase the silicon nanocrystal density, as suggested in the literature, a dip of the oxidized wafer in diluted HF before LPCVD deposition was used, but this step was found to seriously affect the charging properties of the structure.
机译:通过三步工艺制造嵌入在超薄SiO_2层中的硅纳米晶体的二维阵列,以用于硅纳米晶体存储器:(a)隧穿氧化硅的生长;(b)硅的低压化学气相沉积(LPCVD)。薄层非晶硅(α-Si),以及(c)在高温炉中在氮气流下a-Si层进行固相结晶,然后在同一炉中进行热氧化。透射电子显微镜(TEM)用于三层结构的结构表征以及层厚度和硅纳米晶体尺寸的确定,而电容-电压(CV)和电流-电压(IV)测量用于研究充电硅纳米晶体层的性质。为了增加硅纳米晶体的密度,如文献中所建议的,使用了氧化的晶片在LPCVD沉积之前浸入稀释的HF中,但是发现该步骤会严重影响结构的带电性能。

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