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iDP Standard for an Internal Connection in a Large-screen Display

机译：大屏幕显示器内部连接的iDP标准

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This paper provides for a technical overview of iDP (Internal DisplayPort) Standard Ver.1.0. The iDP is an open industry standard developed for transporting a video pixel stream from a TV/monitor controller SOC (system on chip) to a TV/monitor panel TCON within a TV/monitor chassis. This standard leverages the proven DisplayPort technology at its simplest form. Targeted at replacing LVDS, the iDP consists of Main Link and HPD signal, operating without sideband channel. Instead of AUX CH of DisplayPort Standard, the iDP uses HPD pulse to coordinate Link Training; an iDP sink device asserts an HPD pulse to prompt an iDP source device to transmit Link Training patterns over Main Link Nominal iDP link rate of 3.24Gbps/lane enables the transport of FHD240Hz video stream with the pixel bit depth of 30 bits per pixel over 8 lanes (or differential pairs), as opposed to 48 differential pairs of Quad LVDS link. The permitted number of lanes per bank is 1 to 16 lanes inclusive, and the permitted number of banks is 1 or more, depending on a panel configuration. Using data throttling technique, an iDP source device enables an iDP sink device to regenerate the pixel clock synchronously from a link symbol clock as in f_pixel_clock = f_LinkSymbolClock * Mvid/48, where Mvid is an 8-bit integer-value, thus allowing for further simplification of an iDP TCON implementation.
机译：本文提供了iDP（内部DisplayPort）标准Ver.1.0的技术概述。 iDP是一种开放的行业标准，旨在将视频像素流从电视/显示器控制器SOC（片上系统）传输到电视/显示器机箱内的电视/显示器面板TCON。该标准以最简单的形式利用了成熟的DisplayPort技术。 iDP旨在取代LVDS，由主链路和HPD信号组成，无需边带通道即可运行。 iDP使用HPD脉冲代替DisplayPort Standard的AUX CH来协调链接训练; iDP接收器设备发出HPD脉冲，以提示iDP源设备通过主链路标称值传输3.24Gbps / lane的iDP链路速率，从而能够传输FHD240Hz视频流，其像素位深度为每像素30位，超过8个通道（或差分对），而不是四路LVDS链路的48个差分对。每个面板的允许通道数为1到16个通道（含1和16），并且取决于面板配置，允许的通道数为1个或更多。通过使用数据限制技术，iDP源设备使iDP宿设备能够从链接符号时钟同步再生像素时钟，如f_pixel_clock = f_LinkSymbolClock * Mvid / 48，其中Mvid是8位整数值，从而允许进一步简化iDP TCON实施。

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