On fast carry select adders

机译：在快速进位选择加法器上

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme has the same transistor count, without suffering any performance degradation, compared to the Manchester carry chain adder.

著录项

作者
Shamanna, M.; Whitaker, S.;
展开▼
作者单位

展开▼
年度 1992
页码 1-8
总页数 8
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
ADDING CIRCUITS; ARCHITECTURE (COMPUTERS); GATES (CIRCUITS); LOGIC CIRCUITS; TRANSISTOR CIRCUITS; TRANSISTORS; CIRCUIT DIAGRAMS; LOGIC DESIGN; TIME LAG;

机译：添加电路;建筑（计算机）;盖茨（电路）;逻辑电路;晶体管电路;晶体管，电路图;逻辑设计;时间滞后;

相似文献

外文文献
中文文献
专利

1. Design Of Area And Speed Efficient Square Root Carry Select Adder Using Fast Adders [J] . K.Mariya Priyadarshini, N.V.N. Ravi Kiran, N. Tejasri, International Journal of Scientific & Technology Research . 2014,第6期

机译：使用快速加法器设计面积和速度有效的平方根进位选择加法器
2. Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders [J] . Tani Hani Taheri, Zarandi Arezoo Dabaghi, Reshadinezhad Mohammad Reza Microelectronic Engineering . 2019,第Jula期

机译：基于高性能CNTFET的全加法器单元的设计，适用于：携带纹波，进位选择和进位跳过加法器
3. Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders [J] . Tani Hani Taheri, Zarandi Arezoo Dabaghi, Reshadinezhad Mohammad Reza Microelectronic Engineering . 2019,第JULa期

机译：基于高性能CNTFET的全加法器单元的设计，适用于：携带纹波，进位选择和进位跳过加法器
4. Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders [C] . Amelifard, B., Fallah, . 2005

机译：缩小进位选择加法器和纹波进位加法器之间的差距：新型的低功耗高性能加法器
5. Simulation and analysis of high-speed conditional carry select adder. [D] . Ranganadham, Srilatha. 2003

机译：高速条件进位选择加法器的仿真与分析。
6. Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders [O] . P. Balasubramanian, S. Yamashita -1

机译：面积/延迟优化的早期输出异步全加法器和相对定时的纹波进位加法器
7. An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell [O] . Heng You, Weidi Tang, Jia Yuan, 2019

机译：能量和区域高效携带选择加法器双重携带加法器

On fast carry select adders

摘要

著录项

相似文献

相关主题

期刊订阅