首页> 美国政府科技报告 >Technique for Evaluating the Application of the Pin-Level Stuck-at Fault Model to VLSI (Very Large Scale Integrated) Circuits,

【24h】

Technique for Evaluating the Application of the Pin-Level Stuck-at Fault Model to VLSI (Very Large Scale Integrated) Circuits,

机译：针对超大规模集成电路的超高压集成电路应用引脚级卡住故障模型的评估技术，

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.

著录项

作者
palumbo, d. l. finelli, g. b.;
展开▼
作者单位

展开▼
年度 1987
页码 1-45
总页数 45
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Integrated circuits; Very large scale integration; Computers; Error analysis; Evaluation; Fault tolerance; Computerized simulation; Digital systems; Reliability engineering; Statistical analysis; Fault tolerant computing;

机译：集成电路;超大规模集成;计算机;误差分析;评估;容错;计算机仿真;数字系统;可靠性工程;统计分析;容错计算;

相似文献

外文文献
中文文献
专利

1. A test evaluation technique for VLSI circuits using register-transfer level fault modeling [J] . Thaker P.A., Agrawal V.D., Zaghloul M.E. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2003,第8期

机译：使用寄存器传输级故障建模的VLSI电路测试评估技术
2. Synthesis and Fabrication of Novel Polymeric/Organic Materials for Micro/Nano-scale Optical Printed Circuit Board and VLSI Photonic Integrated Circuit Application [J] . El-Hang Lee, In-Joo Chin, Yong Ku Kwon, Diffusion and Defect Data. Solid State Data, Part B. Solid State Phenomena . 2007,第1期

机译：用于微米/纳米级光学印刷电路板和VLSI光子集成电路应用的新型聚合物/有机材料的合成与制备
3. Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models [J] . Lanzerotti M.Y., Fiorenza G., Rand R.A. IEEE transactions on very large scale integration (VLSI) systems . 2004,第12期

机译：解释超大规模集成电路设计的租金规则，并应用于线长分布模型
4. Register-transfer level fault modeling and test evaluation techniques for VLSI circuits [C] . Thaker, P.A., Agrawal, . 2000

机译：用于VLSI电路的寄存器传输级故障建模和测试评估技术
5. Register-transfer level fault modeling and test evaluation technique for VLSI circuits. [D] . Thaker, Pradipkumar Arunbhai. 2000

机译：VLSI电路的寄存器传输级故障建模和测试评估技术。
6. Evaluating an integrated cognitive competencies model to enhance teachers’ application of technology in large-scale educational contexts [O] . João Carlos Wiziack, Vitor Manuel Pereira Duarte dos Santos 2021

机译：评估综合认知能力模型以提高教师在大规模教育背景下的应用
7. A Test Evaluation Technique for VLSI Circuits Using Register-Transfer Level Fault Modeling [O] . Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul 2003

机译：基于寄存器传输级故障建模的VLSI电路测试评估技术
8. A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits [R] . Palumbo, Daniel L., Finelli, George B. 1987

机译：一种评估引脚级固定故障模型在VLsI电路中应用的技术

Technique for Evaluating the Application of the Pin-Level Stuck-at Fault Model to VLSI (Very Large Scale Integrated) Circuits,

摘要

著录项

相似文献

相关主题

期刊订阅